JAJSHP1E July 2014 – June 2022 ADC3221 , ADC3222 , ADC3223 , ADC3224
PRODUCTION DATA
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | HIGH IF MODE0 | 0 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h | W-0h |
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | 0 | W | 0h | Must write 0 |
1 | HIGH IF MODE0 | R/W | 0h | This bit improves HD3 for IF > 100 MHz. 0 = Normal operation For best HD3 at IF > 100 MHz, set HIGH IF MODE[3:0] to 1111. |
0 | 0 | W | 0h | Must write 0 |