The ADC32RF52 provides a total of eight internal single core 1.5 Gsps ADCs. Normal bypass mode uses only two ADC cores (one ADC per channel). However the additional six ADCs can be used to trade off further noise density improvement against additional power consumption. Figure 7-42 shows the internal block diagrams for the digital averaging modes. In averaging mode the output resolution is increased to 16-bit to avoid quantization noise limitation.

In 2x averaging mode (left) one external input is connected to the INx1 input where two ADC cores internally average the input signal. In 4x averaging (right) the signal has to be split externally and connected to both the INx1 and INx2 inputs where four ADC cores internally average the signal.

Figure 7-42 Internal digital averaging (left: 2x, right: 4x)

Table 7-47 provides a trade-off comparison of the 3 different averaging mode options vs the default, non-averaged mode.

Digital averaging improves decorrelated noise contributions by 3 dB per 2x AVG (ideal) while correlated noise does not improve with averaging. Some of the dominant noise sources are correlated (e.g. clock jitter (external or first clock input buffer) or power supply noise) while others (e.g. ADC thermal noise, clock distribution buffers) are decorrelated. illustrates a performance example comparison across averaging options.

SNR: When operating close to ADC fullscale, some of the SNR limitation is due to jitter and hence the SNR improvement won’t reach 3 dB (2x AVG) or 6 dB (4x AVG). As the input fullscale is reduced, the clock jitter contribution to SNR becomes less and the SNR improvement is approaching the ideal 3 dB per 2x AVG. The same phenomenon can be observed when using digital decimation. As the decimation factor increases, the close-in (correlated noise) becomes the more dominating noise unless the input signal amplitude is reduced.

SFDR: The amplitude of low order harmonics (HD2-HD5) and IMD3 typically is very similar across ADCs and thus the improvement with averaging is very small.