SBAS670B July 2014 – April 2017 ADC3441 , ADC3442 , ADC3443 , ADC3444
PRODUCTION DATA.
The ADC344x devices are a high-linearity, ultra-low power, quad-channel, 14-bit, 25-MSPS to 125-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design while the SYSREF input enables complete system synchronization. The ADC344x family supports serial LVDS interface in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 14-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.
The ADC344x analog signal inputs are designed to be driven differentially. Each input pin (INP, INM) must swing symmetrically between (VCM + 0.5 V) and (VCM – 0.5 V), resulting in a 2-VPP (default) differential input swing. The input sampling circuit has a 3-dB bandwidth that extends up to 540 MHz (50-Ω source driving 50-Ω termination between INP and INM).
The device clock inputs may be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to 0.95 V using internal 5-kΩ resistors. The ADC344x self-bias clock inputs may be driven by the transformer-coupled, sine-wave clock source or by the ac-coupled, LVPECL and LVDS clock sources, as shown in Figure 145, Figure 146, and Figure 147. See Figure 148 for details regarding the internal clock buffer.
A single-ended CMOS clock may be ac-coupled to the CLKP input, with CLKM connected to ground with a
0.1-μF capacitor, as shown in Figure 149. However, for best performance the clock inputs must be driven differentially, thereby reducing susceptibility to common-mode noise. For high input frequency sampling, TI recommends using a clock source with low jitter. Band-pass filtering of the clock source may help reduce the effects of jitter. There is no change in performance with a non-50% duty cycle clock input.
The ADC344x has a SYSREF input pin that can be used when the clock-divider feature is used. A logic low-to-high transition on the SYSREF pin aligns the falling edge of the divided clock with the next falling edge of the input clock, essentially resetting the phase of the divided clock, as shown in Figure 150. When multiple ADC344x devices are onboard and the clock divider option is used, the phase of the divided clock among the devices may not be the same. The phase of the divided clock in each device can be synchronized to the common sampling clock by using the SYSREF pins. SYSREF can applied as mono-shot or periodic waveform. When applied as periodic waveform, its period must be integer multiple of period of the divided clock. When not used, the SYSREFP and SYSREFM pins can be connected to AVDD and GND, respectively. Alternatively, the SYSREF buffer inside the device can be powered down using the PDN SYSREF register bit.
The signal-to-noise ratio of the ADC is limited by three different factors, as shown in Equation 1. Quantization noise (typically 86 dB for a 14-bit ADC) and thermal noise limit SNR at low input frequencies while the clock jitter sets SNR for higher input frequencies.
The SNR limitation resulting from sample clock jitter may be calculated with Equation 2.
The total clock jitter (TJitter) has two components: the internal aperture jitter (130 fs for the device) which is set by the noise of the clock input buffer and the external clock. TJitter may be calculated with Equation 3.
External clock jitter may be minimized by using high-quality clock sources and jitter cleaners as well as band-pass filters at the clock input while a faster clock slew rate improves the ADC aperture jitter. The devices have a typical thermal noise of 72.7 dBFS and internal aperture jitter of 130 fs. The SNR, depending on the amount of external jitter for different input frequencies, is shown in Figure 151.
The devices offer two different output format options, thus making interfacing to a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC) easy. Each option may be easily programmed using the serial interface, as shown in Table 3. The output interface options are:
INTERFACE OPTIONS | SERIALIZATION | RECOMMENDED SAMPLING FREQUENCY (MSPS) | BIT CLOCK FREQUENCY (MHz) | FRAME CLOCK FREQUENCY (MHz) | SERIAL DATA RATE (Mbps) | |
---|---|---|---|---|---|---|
MINIMUM | MAXIMUM | |||||
1-wire | 14x | 15(1) | — | 105 | 15 | 210 |
— | 80 | 560 | 80 | 1120 | ||
2-wire (default after reset) | 7x | 20(1) | — | 70 | 10 | 140 |
— | 125 | 437.5 | 62.5 | 875 |
In this interface option, the device outputs the data of each ADC serially on a single LVDS pair (one-wire). The data are available at the rising and falling edges of the bit clock (DDR bit clock). The ADC outputs a new word at the rising edge of every frame clock, starting with the LSB. The data rate is 14x sample frequency (14x serialization).
The two-wire interface is recommended for sampling frequencies above 65 MSPS. The output data rate is 7x sample frequency because seven data bits are output every clock cycle on each differential pair. Each ADC sample is sent over the two wires with the seven MSBs on Dx1P, Dx1M and the seven LSBs on Dx0P, Dx0M, as shown in Figure 152.
The devices are equipped with an internal divider on the clock input. The clock divider allows operation with a faster input clock, thus simplifying the system clock distribution design. The clock divider may be bypassed for operation with a 125-MHz clock while the divide-by-2 option supports a maximum input clock of 250 MHz and the divide-by-4 option provides a maximum input clock frequency of 500 MHz.
The devices are equipped with an internal chopper front-end. Enabling the chopper function swaps the ADC noise spectrum by shifting the 1/f noise from dc to fS / 2. Figure 153 shows the noise spectrum with the chopper off and Figure 154 shows the noise spectrum with the chopper on. This function is especially useful in applications requiring good ac performance at low input frequencies or in dc-coupled applications. The chopper may be enabled through SPI register writes and is recommended for input frequencies below 30 MHz. The chopper function creates a spur at fS / 2 that must be filtered out digitally.
fS = 125 MSPS, SNR = 72.7 dBFS, fIN = 10 MHz, SFDR = 94 dBc |
fS = 125 MSPS, SNR = 72.7 dBFS, fIN = 10 MHz, SFDR = 94 dBc |
The ADC344x power-down functions may be controlled either through the parallel control pin (PDN) or through an SPI register setting (see register 15h). The PDN pin may also be configured through SPI to a global power-down or standby functionality, as shown in Table 4.
FUNCTION | POWER CONSUMPTION (mW) | WAKE-UP TIME (µs) |
---|---|---|
Global power-down | 5 | 85 |
Standby | 45 | 35 |
The ADC344x family uses an internal dither algorithm to achieve high SFDR and a clean spectrum. However, the dither algorithm marginally degrades SNR, creating a trade-off between SNR and SFDR. If desired, the dither algorithm may be turned off by using the DIS DITH CHx registers bits. Figure 155 and Figure 156 show the effect of using dither algorithms.
SFDR = 98 dBc, SNR = 73.1 dBFS, SINAD = 73 dBFS, THD = 97 dBc, HD2 = 110.0 dBc, HD3 = 98 dBc, SFDR = 100 dBc (excluding HD2, HD3) |
SFDR = 90 dBc, SNR = 73.5 dBFS, SINAD = 73.2 dBFS, THD = 88 dBc, HD2 = 90 dBc, HD3 = 100 dBc, SFDR = 92 dBc (excluding HD2, HD3) |
Table 5 lists the location, value, and functions of performance mode registers in the device.
MODE | LOCATION | FUNCTION |
---|---|---|
Special modes | Registers 139 (bit 3), 239 (bit 3), 439 (bit 3), and 539 (bit 3) | Always write 1 for best performance. |
Disable dither | Registers 1 (bits 7-0), 134 (bits 5 and 3), 234 (bits 5 and 3), 434 (bits 5 and 3), and 534 (bits 5 and 3) |
Disables the dither to improve SNR. |
Disable chopper | Registers 122 (bit 1), 222 (bit 1), 422 (bit 1), and 522 (bit 1) | Disables the chopper (shifts the 1/f noise floor at dc). |
High IF modes | Registers 11Dh (bit 1), 21Dh (bit 1), 41Dh (bit 1), 51Dh (bit 1), 308h (bits 7-6) and 608h (bits 7-6) | Improves HD3 by a couple of dB for IF > 100 MHz |
The ADC344x device may be configured using a serial programming interface, as described in this section.
The device has a set of internal registers that may be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock), SDATA (serial interface data), and SDOUT (serial interface data output) pins. Serially shifting bits into the device is enabled when SEN is low. Serial data SDATA are latched at every SCLK rising edge when SEN is active (low). The serial data are loaded into the register at every 24th SCLK rising edge when SEN is low. When the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data may be loaded in multiples of 24-bit words within a single active SEN pulse. The interface may function with SCLK frequencies from 20 MHz down to very low speeds (of a few hertz) and also with a non-50% SCLK duty cycle.
After power-up, the internal registers must be initialized to their default values through a hardware reset by applying a high pulse on the RESET pin (of durations greater than 10 ns), as shown in Figure 157. If required, the serial interface registers may be cleared during operation either:
The device internal register may be programmed with these steps:
Figure 157 and Table 6 show the timing requirements for the serial register write operation.
MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|
fSCLK | SCLK frequency (equal to 1 / tSCLK) | > DC | 20 | MHz | |
tSLOADS | SEN to SCLK setup time | 25 | ns | ||
tSLOADH | SCLK to SEN hold time | 25 | ns | ||
tDSU | SDIO setup time | 25 | ns | ||
tDH | SDIO hold time | 25 | ns |
The device includes a mode where the contents of the internal registers may be read back using the SDOUT pin. This readback mode may be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC. The procedure to read the contents of the serial registers is as follows:
When READOUT is disabled, the SDOUT pin is in a high-impedance mode. If serial readout is not used, the SDOUT pin must float. Figure 158 shows a timing diagram of the serial register read operation. Data appear on the SDOUT pin at the SCLK falling edge with an approximate delay (tSD_DELAY) of 20 ns, as shown in Figure 159.
Power-up begins with the application of AVDD and DVDD. The exact sequencing and ramp rate of AVDD and DVDD are not important as long as the parameters in Table 7 are met.
After power-up, the RESET pin must be pulsed high to reset the internal registers to the default values. Figure 160 and Table 7 show a power-up sequence.
During operation, the device registers can be restored to the default values by either pulsing the RESET pin high or by issuing a software reset via the SPI interface. A software reset can be issued by writing bit 0 of register 06h high. This bit is self-clearing.
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
t1 | AVDD supply power-up ramp time | 10 | ms | ||
t2 | DVDD supply power-up ramp time | 10 | ms | ||
t3 | AVDD to DVDD power-up delay | -10 | 10 | ms | |
t4 | Device power-up to RESET assertion | 1 | ms | ||
t5 | RESET assertion duration | 10 | ns | ||
t6 | RESET deassertion to SEN assertion | 10 | µs | ||
t7 | RESET deassertion to valid conversions | 150 | µs | ||
t8 | CLK stable frequency to valid conversions | 150 | µs |
After the power supplies are valid, enable the sample clock. The sampling clock can be enabled before or after reset, but conversions are not valid until at least a minimum time after reset and the time that the sample clock reaches a stable frequency, as shown in Table 7.
Before using samples from the device, a minimum register write sequence must be applied, as described in Table 8. Apply this register write sequence after any further application of the hardware or software reset.
ADDRESS | DATA | NOTE |
---|---|---|
139h | 08h | Channel A - best performance default |
439h | 08h | Channel B - best performance default |
539h | 08h | Channel C - best performance default |
239h | 08h | Channel D - best performance default |
137h | 40h | ADC core latch reset |
437h | 40h | |
537h | 40h | |
237h | 40h | |
137h | 00h | |
437h | 00h | |
537h | 00h | |
237h | 00h |
These register writes configure the optimal settings for ADC performance and apply a reset to the internal latches inside the ADC core that are not part of the device reset function. After the register writes of Table 8 are written, any use-case-specific registers must be applied before using the conversion values.
REGISTER ADDRESS, A[13:0] (Hex) |
REGISTER DATA | |||||||
---|---|---|---|---|---|---|---|---|
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
Register 01h | DIS DITH CHA | DIS DITH CHB | DIS DITH CHC | DIS DITH CHD | ||||
Register 03h | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ODD EVEN |
Register 04h | 0 | 0 | 0 | 0 | 0 | 0 | 0 | FLIP WIRE |
Register 05h | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1W-2W |
Register 06h | 0 | 0 | 0 | 0 | 0 | 0 | TEST PATTERN EN | RESET |
Register 07h | 0 | 0 | 0 | 0 | 0 | 0 | 0 | OVR ON LSB |
Register 09h | 0 | 0 | 0 | 0 | 0 | 0 | ALIGN TEST PATTERN | DATA FORMAT |
Register 0Ah | CHA TEST PATTERN | CHB TEST PATTERN | ||||||
Register 0Bh | CHC TEST PATTERN | CHD TEST PATTERN | ||||||
Register 13h | 0 | 0 | 0 | 0 | 0 | 0 | LOW SPEED ENABLE | |
Register 0Eh | CUSTOM PATTERN[13:6] | |||||||
Register 0Fh | CUSTOM PATTERN[5:0] | 0 | 0 | |||||
Register 15h | CHA PDN | CHB PDN | CHC PDN | CHD PDN | STANDBY | GLOBAL PDN | 0 | CONFIG PDN PIN |
Register 25h | LVDS SWING | |||||||
Register 27h | CLK DIV | 0 | 0 | 0 | 0 | 0 | 0 | |
Register 11Dh | 0 | 0 | 0 | 0 | 0 | 0 | HIGH IF MODE0 | 0 |
Register 122h | 0 | 0 | 0 | 0 | 0 | 0 | DIS CHOP CHA | 0 |
Register 134h | 0 | 0 | DIS DITH CHA | 0 | DIS DITH CHA | 0 | 0 | 0 |
Register 139h | 0 | 0 | 0 | 0 | SP1 CHA | 0 | 0 | 0 |
Register 21Dh | 0 | 0 | 0 | 0 | 0 | 0 | HIGH IF MODE1 | 0 |
Register 222h | 0 | 0 | 0 | 0 | 0 | 0 | DIS CHOP CHD | 0 |
Register 234h | 0 | 0 | DIS DITH CHD | 0 | DIS DITH CHD | 0 | 0 | 0 |
Register 239h | 0 | 0 | 0 | 0 | SP1 CHD | 0 | 0 | 0 |
Register 308 | HIGH IF MODE <5:4> | 0 | 0 | 0 | 0 | 0 | 0 | |
Register 41Dh | 0 | 0 | 0 | 0 | 0 | 0 | HIGH IF MODE2 | 0 |
Register 422h | 0 | 0 | 0 | 0 | 0 | 0 | DIS CHOP CHB | 0 |
Register 434h | 0 | 0 | DIS DITH CHB | 0 | DIS DITH CHB | 0 | 0 | 0 |
Register 439h | 0 | 0 | 0 | 0 | SP1 CHB | 0 | 0 | 0 |
Register 51Dh | 0 | 0 | 0 | 0 | 0 | 0 | HIGH IF MODE3 | 0 |
Register 522h | 0 | 0 | 0 | 0 | 0 | 0 | DIS CHOP CHC | 0 |
Register 534h | 0 | 0 | DIS DITH CHC | 0 | DIS DITH CHC | 0 | 0 | 0 |
Register 539h | 0 | 0 | 0 | 0 | SP1 CHC | 0 | 0 | 0 |
Register 608h | HIGH IF MODE <7:6> | 0 | 0 | 0 | 0 | 0 | 0 | |
Register 70Ah | 0 | 0 | 0 | 0 | 0 | 0 | 0 | PDN SYSREF |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIS DITH CHA | DIS DITH CHB | DIS DITH CHC | DIS DITH CHD | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | DIS DITH CHA | R/W | 0h | These bits enable or disable the on-chip dither. Control this bit along with bits 5 and 3 of register 134h. 00 = Default 11 = Dither is disabled for channel A. In this mode, SNR typically improves by 0.5 dB at 70 MHz. |
5-4 | DIS DITH CHB | R/W | 0h | These bits enable or disable the on-chip dither. Control this bit along with bits 5 and 3 of register 434h. 00 = Default 11 = Dither is disabled for channel B. In this mode, SNR typically improves by 0.5 dB at 70 MHz. |
3-2 | DIS DITH CHC | R/W | 0h | These bits enable or disable the on-chip dither. Control this bit along with bits 5 and 3 of register 534h. 00 = Default 11 = Dither is disabled for channel B. In this mode, SNR typically improves by 0.5 dB at 70 MHz. |
1-0 | DIS DITH CHD | R/W | 0h | These bits enable or disable the on-chip dither. Control this bit along with bits 5 and 3 of register 234h. 00 = Default 11 = Dither is disabled for channel B. In this mode, SNR typically improves by 0.5 dB at 70 MHz. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | ODD EVEN |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-1 | 0 | W | 0h | Must write 0. |
0 | ODD EVEN | R/W | 0h | This bit selects the bit sequence on the output wires (in 2-wire mode only). 0 = Bits 0, 1, 2, and so forth appear on wire-0; bits 7, 8, 9, and so forth appear on wire-1. 1 = Bits 0, 2, 4, and so forth appear on wire-0; bits 1, 3, 5, and so forth appear on wire-1. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | FLIP WIRE |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-1 | 0 | W | 0h | Must write 0. |
0 | FLIP WIRE | R/W | 0h | This bit flips the data on the output wires. Valid only in two wire configuration. 0 = Default 1 = Data on output wires is flipped. Pin D0x becomes D1x, and vice versa. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 1W-2W |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-1 | 0 | W | 0h | Must write 0. |
0 | 1W-2W | R/W | 0h | This bit transmits output data on either one or two wires. 0 = Output data are transmitted on two wires (Dx0P, Dx0M and Dx1P, Dx1M) 1 = Output data are transmitted on one wire (Dx0P, Dx0M). In this mode, the recommended fS is less than 80 MSPS. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | TEST PATTERN EN | RESET |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | 0 | W | 0h | Must write 0. |
1 | TEST PATTERN EN | R/W | 0h | Enables test pattern selection for the digital outputs. 0 = Normal output 1 = Test pattern output enabled |
0 | RESET | R/W | 0h | Software reset applied. This bit resets all internal registers to the default values and self-clears to 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | OVR ON LSB |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-1 | 0 | W | 0h | Must write 0. |
0 | OVR ON LSB | R/W | 0h | OVR information on the LSB bits. 0 = Output data bit 0 functions as the LSB of the 14-bit data 1 = Output data bit 0 carries the overrange (OVR) information. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | ALIGN TEST PATTERN | DATA FORMAT |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | 0 | W | 0h | Must write 0. |
1 | ALIGN TEST PATTERN | R/W | 0h | This bit aligns the test patterns across the outputs of both channels. 0 = Test patterns of both channels are free running 1 = Test patterns of both channels are aligned |
0 | DATA FORMAT | R/W | 0h | Digital output data format. 0 = Twos complement 1 = Offset binary |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CHA TEST PATTERN | CHB TEST PATTERN | ||||||
R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | CHA TEST PATTERN | R/W | 0h | These bits control the test pattern for channel A after the TEST PATTERN EN bit is set. 0000 = Normal operation 0001 = All 0's 0010 = All 1's 0011 = Toggle pattern: data alternate between 10101010101010 and 01010101010101 0100 = Digital ramp: data increment by 1 LSB every clock cycle from code 0 to 16383 0101 = Custom pattern: output data are the same as programmed by the CUSTOM PATTERN register bits 0110 = Deskew pattern: data are 2AAAh 1000 = PRBS pattern: data are a sequence of pseudo random numbers 1001 = 8-point sine-wave: data are a repetitive sequence of the following eight numbers that form a sine-wave: 0, 2399, 8192, 13984, 16383, 13984, 8192, 2399. Others = Do not use |
3-0 | CHB TEST PATTERN | R/W | 0h | These bits control the test pattern for channel B after the TEST PATTERN EN bit is set. 0000 = Normal operation 0001 = All 0's 0010 = All 1's 0011 = Toggle pattern: data alternate between 10101010101010 and 01010101010101 0100 = Digital ramp: data increment by 1 LSB every clock cycle from code 0 to 16383 0101 = Custom pattern: output data are the same as programmed by the CUSTOM PATTERN register bits 0110 = Deskew pattern: data are 2AAAh 1000 = PRBS pattern: data are a sequence of pseudo random numbers 1001 = 8-point sine-wave: data are a repetitive sequence of the following eight numbers that form a sine-wave: 0, 2399, 8192, 13984, 16383, 13984, 8192, 2399. Others = Do not use |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CHC TEST PATTERN | CHD TEST PATTERN | ||||||
R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | CHC TEST PATTERN | R/W | 0h | These bits control the test pattern for channel C after the TEST PATTERN EN bit is set. 0000 = Normal operation 0001 = All 0's 0010 = All 1's 0011 = Toggle pattern: data alternate between 10101010101010 and 01010101010101 0100 = Digital ramp: data increment by 1 LSB every clock cycle from code 0 to 16383 0101 = Custom pattern: output data are the same as programmed by the CUSTOM PATTERN register bits 0110 = Deskew pattern: data are 2AAAh 1000 = PRBS pattern: data are a sequence of pseudo random numbers 1001 = 8-point sine-wave: data are a repetitive sequence of the following eight numbers that form a sine-wave: 0, 2399, 8192, 13984, 16383, 13984, 8192, 2399. Others = Do not use |
3-0 | CHD TEST PATTERN | R/W | 0h | These bits control the test pattern for channel D after the TEST PATTERN EN bit is set. 0000 = Normal operation 0001 = All 0's 0010 = All 1's 0011 = Toggle pattern: data alternate between 10101010101010 and 01010101010101 0100 = Digital ramp: data increment by 1 LSB every clock cycle from code 0 to 16383 0101 = Custom pattern: output data are the same as programmed by the CUSTOM PATTERN register bits 0110 = Deskew pattern: data are 2AAAh 1000 = PRBS pattern: data are a sequence of pseudo random numbers 1001 = 8-point sine-wave: data are a repetitive sequence of the following eight numbers that form a sine-wave: 0, 2399, 8192, 13984, 16383, 13984, 8192, 2399. Others = Do not use |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | LOW SPEED ENABLE | |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | 0 | W | 0h | Must write 0. |
1-0 | LOW SPEED ENABLE | R/W | 0h | Enables low speed operation in 1-wire and 2-wire mode. Depending upon sampling frequency, write this bit as per Table 20. |
fS, MSPS | REGISTER BIT LOW SPEED ENABLE | |||
---|---|---|---|---|
MIN | MAX | 1-WIRE MODE | 2-WIRE MODE | |
25 | 125 | 00 | 00 | |
20 | 25 | 00 | 10 | |
15 | 20 | 10 | Not supported |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CUSTOM PATTERN[13:6] | |||||||
R/W-0h |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | CUSTOM PATTERN[13:6] | R/W | 0h | These bits set the 14-bit custom pattern (bits 13-6) for all channels. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CUSTOM PATTERN[5:0] | 0 | 0 | |||||
R/W-0h | W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | CUSTOM PATTERN[5:0] | R/W | 0h | These bits set the 14-bit custom pattern (bits 5-0) for all channels. |
1-0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CHA PDN | CHB PDN | CHC PDN | CHD PDN | STANDBY | GLOBAL PDN | 0 | CONFIG PDN PIN |
W-0h | R/W-0h | R/W-0h | W-0h | R/W-0h | R/W-0h | W-0h | R/W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | CHA PDN | W | 0h | 0 = Normal operation 1 = Power-down channel A |
6 | CHB PDN | R/W | 0h | 0 = Normal operation 1 = Power-down channel B |
5 | CHC PDN | R/W | 0h | 0 = Normal operation 1 = Power-down channel C |
4 | CHD PDN | W | 0h | 0 = Normal operation 1 = Power-down channel D |
3 | STANDBY | R/W | 0h | ADCs of both channels enter standby. 0 = Normal operation 1 = Standby |
2 | GLOBAL PDN | R/W | 0h | 0 = Normal operation 1 = Global power-down |
1 | 0 | W | 0h | Must write 0. |
0 | CONFIG PDN PIN | R/W | 0h | This bit configures the PDN pin as either a global power-down or standby pin. 0 = Logic high voltage on PDN pin sends the device into global power-down 1 = Logic high voltage on PDN pin sends the device into standby |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LVDS SWING | |||||||
R/W-0h |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | LVDS SWING | R/W | 0h | These bits control the swing of the LVDS outputs (including the data output, bit clock, and frame clock). |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLK DIV | 0 | 0 | 0 | 0 | 0 | 0 | |
R/W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | CLK DIV | R/W | 0h | Internal clock divider for the input sampling clock. 00 = Divide-by-1 01 = Divide-by-1 10 = Divide-by-2 11 = Divide-by-4 |
5-0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | HIGH IF MODE0 | 0 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | 0 | W | 0h | Must write 0. |
1 | HIGH IF MODE0 | Set the HIGH IF MODE[7:0] bits together to 1111. Improves HD3 by a couple of dB for IF > 100 MHz. |
||
0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | DIS CHOP CHA | 0 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | 0 | W | 0h | Must write 0. |
1 | DIS CHOP CHA | R/W | 0h | Disables the chopper. Set this bit to shift 1/f noise floor at dc. 0 = 1/f noise floor is centered at fS / 2 (default) 1 = Chopper mechanism is disabled; 1/f noise floor is centered at dc |
0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | DIS DITH CHA | 0 | DIS DITH CHA | 0 | 0 | 0 |
W-0h | W-0h | R/W-0h | W-0h | R/W-0h | W-0h | W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | 0 | W | 0h | Must write 0. |
5 | DIS DITH CHA | R/W | 0h | Set this bit with bits 7 and 6 of register 01h. 00 = Default 11 = Dither is disabled for channel A. In this mode, SNR typically improves by 0.5 dB at 70 MHz. |
4 | 0 | W | 0h | Must write 0. |
3 | DIS DITH CHA | R/W | 0h | Set this bit with bits 7 and 6 of register 01h. 00 = Default 11 = Dither is disabled for channel A. In this mode, SNR typically improves by 0.5 dB at 70 MHz. |
2-0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | SP1 CHA | 0 | 0 | 0 |
W-0h | W-0h | W-0h | W-0h | R/W-0h | W-0h | W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | 0 | W | 0h | Must write 0. |
3 | SP1 CHA | R/W | 0h | Special mode for best performance on channel A. Always write 1 after reset. |
2-0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | HIGH IF MODE1 | 0 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | 0 | W | 0h | Must write 0. |
1 | HIGH IF MODE1 | Set the HIGH IF MODE[7:0] bits together to 1111. Improves HD3 by a couple of dB for IF > 100 MHz. |
||
0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | DIS CHOP CHD | 0 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | 0 | W | 0h | Must write 0. |
1 | DIS CHOP CHD | R/W | 0h | Disables the chopper. Set this bit to shift 1/f noise floor at dc. 0 = 1/f noise floor is centered at fS / 2 (default) 1 = Chopper mechanism is disabled; 1/f noise floor is centered at dc |
0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | DIS DITH CHD | 0 | DIS DITH CHD | 0 | 0 | 0 |
W-0h | W-0h | R/W-0h | W-0h | R/W-0h | W-0h | W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | 0 | W | 0h | Must write 0. |
5 | DIS DITH CHD | R/W | 0h | Set this bit with bits 1 and 0 of register 01h. 00 = Default 11 = Dither is disabled for channel D. In this mode, SNR typically improves by 0.5 dB at 70 MHz. |
4 | 0 | W | 0h | Must write 0. |
3 | DIS DITH CHD | R/W | 0h | Set this bit with bits 1 and 0 of register 01h. 00 = Default 11 = Dither is disabled for channel D. In this mode, SNR typically improves by 0.5 dB at 70 MHz. |
2-0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | SP1 CHD | 0 | 0 | 0 |
W-0h | W-0h | W-0h | W-0h | R/W-0h | W-0h | W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | 0 | W | 0h | Must write 0. |
3 | SP1 CHD | R/W | 0h | Special mode for best performance on channel D. Always write 1 after reset. |
2-0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HIGH IF MODE<5:4> | 0 | 0 | 0 | 0 | 0 | 0 | |
W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | HIGH IF MODE<5:4> | W | 0h | Set the HIGH IF MODE[7:0] bits together to FFh. Improves HD3 by a couple of dB for IF > 100 MHz. |
5-0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | HIGH IF MODE2 | 0 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | 0 | W | 0h | Must write 0. |
1 | HIGH IF MODE2 | Set the HIGH IF MODE[7:0] bits together to FFh. Improves HD3 by a couple of dB for IF > 100 MHz. |
||
0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | DIS CHOP CHB | 0 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | 0 | W | 0h | Must write 0. |
1 | DIS CHOP CHB | R/W | 0h | Disables the chopper. Set this bit to shift 1/f noise floor at dc. 0 = 1/f noise floor is centered at fS / 2 (default) 1 = Chopper mechanism is disabled; 1/f noise floor is centered at dc |
0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | DIS DITH CHB | 0 | DIS DITH CHB | 0 | 0 | 0 |
W-0h | W-0h | R/W-0h | W-0h | R/W-0h | W-0h | W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | 0 | W | 0h | Must write 0. |
5 | DIS DITH CHB | R/W | 0h | Set this bit with bits 5 and 4 of register 01h. 00 = Default 11 = Dither is disabled for channel B. In this mode, SNR typically improves by 0.5 dB at 70 MHz. |
4 | 0 | W | 0h | Must write 0. |
3 | DIS DITH CHB | R/W | 0h | Set this bit with bits 5 and 4 of register 01h. 00 = Default 11 = Dither is disabled for channel B. In this mode, SNR typically improves by 0.5 dB at 70 MHz. |
2-0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | SP1 CHB | 0 | 0 | 0 |
W-0h | W-0h | W-0h | W-0h | R/W-0h | W-0h | W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | 0 | W | 0h | Must write 0. |
3 | SP1 CHB | R/W | 0h | Special mode for best performance on channel B. Always write 1 after reset. |
2-0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | HIGH IF MODE3 | 0 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | 0 | W | 0h | Must write 0. |
1 | HIGH IF MODE3 | Set the HIGH IF MODE[7:0] bits together to FFh. Improves HD3 by a couple of dB for IF > 100 MHz. |
||
0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | DIS CHOP CHC | 0 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | 0 | W | 0h | Must write 0. |
1 | DIS CHOP CHC | R/W | 0h | Disables the chopper. Set this bit to shift 1/f noise floor at dc. 0 = 1/f noise floor is centered at fS / 2 (default) 1 = Chopper mechanism is disabled; 1/f noise floor is centered at dc |
0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | DIS DITH CHC | 0 | DIS DITH CHC | 0 | 0 | 0 |
W-0h | W-0h | R/W-0h | W-0h | R/W-0h | W-0h | W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | 0 | W | 0h | Must write 0. |
5 | DIS DITH CHC | R/W | 0h | Set this bit with bits 3 and 2 of register 01h. 00 = Default 11 = Dither is disabled for channel C. In this mode, SNR typically improves by 0.5 dB at 70 MHz. |
4 | 0 | W | 0h | Must write 0. |
3 | DIS DITH CHC | R/W | 0h | Set this bit with bits 3 and 2 of register 01h. 00 = Default 11 = Dither is disabled for channel C. In this mode, SNR typically improves by 0.5 dB at 70 MHz. |
2-0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | SP1 CHC | 0 | 0 | 0 |
W-0h | W-0h | W-0h | W-0h | R/W-0h | W-0h | W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | 0 | W | 0h | Must write 0. |
3 | SP1 CHC | R/W | 0h | Special mode for best performance on channel C. Always write 1 after reset. |
2-0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HIGH IF MODE<7:6> | 0 | 0 | 0 | 0 | 0 | 0 | |
W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | HIGH IF MODE<7:6> | Set the HIGH IF MODE[7:0] bits together to FFh. Improves HD3 by a couple of dB for IF > 100 MHz. |
||
5-0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | PDN SYSREF |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-1 | 0 | W | 0h | Must write 0. |
0 | PDN SYSREF | R/W | 0h | If the SYSREF pins are not used in the system, the SYSREF buffer must be powered down by setting this bit. 0 = Normal operation 1 = Powers down the SYSREF buffer |