JAJSJC8C
July 2020 – December 2022
ADC3541
,
ADC3542
,
ADC3543
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics - Power Consumption
6.6
Electrical Characteristics - DC Specifications
6.7
Electrical Characteristics - AC Specifications ADC3541
6.8
Electrical Characteristics - AC Specifications ADC3542
6.9
Electrical Characteristics - AC Specifications ADC3543
6.10
Timing Requirements
6.11
Typical Characteristics: ADC3541
6.12
Typical Characteristics: ADC3542
6.13
Typical Characteristics: ADC3543
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Analog Input
8.3.1.1
Analog Input Bandwidth
8.3.1.2
Analog Front End Design
8.3.1.2.1
Sampling Glitch Filter Design
8.3.1.2.2
Single Ended Input
8.3.1.2.3
Analog Input Termination and DC Bias
8.3.1.2.3.1
AC-Coupling
8.3.1.2.3.2
DC-Coupling
8.3.1.3
Auto-Zero Feature
8.3.2
Clock Input
8.3.2.1
Single Ended vs Differential Clock Input
8.3.2.2
Signal Acquisition Time Adjust
8.3.3
Voltage Reference
8.3.3.1
Internal voltage reference
8.3.3.2
External voltage reference (VREF)
8.3.3.3
External voltage reference with internal buffer (REFBUF)
8.3.4
Digital Down Converter
8.3.4.1
Digital Filter Operation
8.3.4.2
FS/4 Mixing with Real Output
8.3.4.3
Numerically Controlled Oscillator (NCO) and Digital Mixer
8.3.4.4
Decimation Filter
8.3.4.5
SYNC
8.3.4.6
Output Formatting with Decimation
8.3.4.6.1
Parallel CMOS
8.3.4.6.2
Serialized CMOS Interface
8.3.5
Digital Interface
8.3.5.1
Parallel CMOS Output
8.3.5.2
Serialized CMOS output
8.3.5.2.1
SDR Output Clocking
8.3.5.3
Output Data Format
8.3.5.4
Output Formatter
8.3.5.5
Output Bit Mapper
8.3.5.6
Output Interface/Mode Configuration
8.3.5.6.1
Configuration Example
8.3.6
Test Pattern
8.4
Device Functional Modes
8.4.1
Normal operation
8.4.2
Power Down Options
8.5
Programming
8.5.1
Configuration using PINs only
8.5.2
Configuration Using the SPI Interface
8.5.2.1
Register Write
8.5.2.2
Register Read
8.6
Register Map
8.6.1
Detailed Register Description
9
Application Information Disclaimer
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Input Signal Path
9.2.2.2
Sampling Clock
9.2.2.3
Voltage Reference
9.2.3
Application Curves
9.3
Initialization Set Up
9.3.1
Register Initialization During Operation
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Receiving Notification of Documentation Updates
12.2
サポート・リソース
12.3
Trademarks
12.4
静電気放電に関する注意事項
12.5
用語集
13
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RSB|40
MPQF185C
サーマルパッド・メカニカル・データ
RSB|40
QFND255H
発注情報
jajsjc8c_oa
jajsjc8c_pm
1
特長
14 ビット 10/25/65MSPS ADC
ノイズ・フロア:–155dBFS/Hz
最適な電力スケーリングで超低消費電力を実現:
35mW (10MSPS)~84mW (65SPS)
レイテンシ:1 クロック・サイクル
INL:±0.6LSB、DNL:±0.1LSB
基準電圧:外部または内部
入力周波数帯域:900MHz (3dB)
産業用温度範囲:–40℃~+105℃
オンチップ・デジタル・フィルタ (オプション)
デシメーション比:2、4、8、16、32
32 ビット NCO
SDR/DDR およびシリアル CMOS インターフェイス
小型サイズ:40-WQFN (5mm × 5mm) パッケージ
1.8V 単電源
スペクトル性能 (f
IN
= 10MHz):
SNR79.0dBFS
SFDR:87dBc HD2、HD3
SFDR:99dBFS の最大スプリアス
スペクトル性能 (f
IN
= 64MHz):
SNR:78.0dBFS
SFDR70dBc HD2、HD3
SFDR91dBFS の最大スプリアス