JAJSJC8C July 2020 – December 2022 ADC3541 , ADC3542 , ADC3543
PRODUCTION DATA
In serialized CMOS mode, the ADC354x device supports complex decimation output Figure 8-38 and real decimation output Figure 8-39. The examples are shown for 16-bit output for 2-wire (8x serialization) and 1-wire (16x serialization).
Table 8-6 illustrates the output interface data rate along with the corresponding DCLK/DCLKIN and FCLK frequencies based on output resolution (R), number of serial CMOS lanes (L) and complex decimation setting (N).
Furthermore the table shows an actual lane rate example for the 2- and 1- wire interface, 16-bit output resolution and complex decimation by 16.
DECIMATION SETTING | ADC SAMPLING RATE | OUTPUT RESOLUTION | # of WIRES | FCLK | DCLKIN, DCLK | DOUT |
---|---|---|---|---|---|---|
N | FS | R | L | FS / N | [DOUT] / 2 | FS x 2 x R / L / N |
16 | 65 MSPS | 16 | 2 | 4.0625 MHz | 32.5 MHz | 65 MHz |
1 | 65 MHz | 130 MHz |
Table 8-7 illustrates the output interface data rate along with the corresponding DCLK/DCLKIN and FCLK frequencies based on output resolution (R), number of serial CMOS lanes (L) and real decimation setting (M).
Furthermore the table shows an actual lane rate example for the 2- and 1-wire interface, 16-bit output resolution and real decimation by 16.
DECIMATION SETTING | ADC SAMPLING RATE | OUTPUT RESOLUTION | # of WIRES | FCLK | DCLKIN, DCLK | DOUT |
---|---|---|---|---|---|---|
M | FS | R | L | FS / M / 2 (L = 2) FS / M (L = 1) | [DOUT] / 2 | FS x R / L / M |
16 | 65 MSPS | 16 | 2 | 2.03125 MHz | 16.25 MHz | 32.5 MHz |
1 | 4.0625 MHz | 32.5 MHz | 65 MHz |