JAJSL69A February   2021  – October 2022 ADC3581 , ADC3582 , ADC3583

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications
    8. 6.8  Timing Requirements
    9. 6.9  Typical Characteristics - ADC3581
    10. 6.10 Typical Characteristics - ADC3582
    11. 6.11 Typical Characteristics - ADC3583
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Bandwidth
        2. 8.3.1.2 Analog Front End Design
          1. 8.3.1.2.1 Sampling Glitch Filter Design
          2. 8.3.1.2.2 Analog Input Termination and DC Bias
            1. 8.3.1.2.2.1 AC-Coupling
            2. 8.3.1.2.2.2 DC-Coupling
        3. 8.3.1.3 Auto-Zero Feature
      2. 8.3.2 Clock Input
        1. 8.3.2.1 Single Ended vs Differential Clock Input
        2. 8.3.2.2 Signal Acquisition Time Adjust
      3. 8.3.3 Voltage Reference
        1. 8.3.3.1 Internal voltage reference
        2. 8.3.3.2 External voltage reference (VREF)
        3. 8.3.3.3 External voltage reference with internal buffer (REFBUF)
      4. 8.3.4 Digital Down Converter
        1. 8.3.4.1 DDC MUX for Dual Band Decimation
        2. 8.3.4.2 Digital Filter Operation
        3. 8.3.4.3 FS/4 Mixing with Real Output
        4. 8.3.4.4 Numerically Controlled Oscillator (NCO) and Digital Mixer
        5. 8.3.4.5 Decimation Filter
        6. 8.3.4.6 SYNC
        7. 8.3.4.7 Output Formatting with Decimation
      5. 8.3.5 Digital Interface
        1. 8.3.5.1 Output Formatter
        2. 8.3.5.2 Output Scrambler
        3. 8.3.5.3 Output Bit Mapper
        4. 8.3.5.4 Output Interface/Mode Configuration
          1. 8.3.5.4.1 Configuration Example
        5. 8.3.5.5 Output Data Format
      6. 8.3.6 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 Power Down Options
    5. 8.5 Programming
      1. 8.5.1 Configuration using PINs only
      2. 8.5.2 Configuration using the SPI interface
        1. 8.5.2.1 Register Write
        2. 8.5.2.2 Register Read
    6. 8.6 Register Map
      1. 8.6.1 Detailed Register Description
  9. 9 Application Information Disclaimer
    1. 9.1 Typical Application
      1. 9.1.1 Design Requirements
      2. 9.1.2 Detailed Design Procedure
        1. 9.1.2.1 Input Signal Path
        2. 9.1.2.2 Sampling Clock
        3. 9.1.2.3 Voltage Reference
      3. 9.1.3 Application Curves
    2. 9.2 Initialization Set Up
      1. 9.2.1 Register Initialization During Operation
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Electrical Characteristics - DC Specifications

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, 1.6 V external reference, and –1-dBFS differential input, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC ACCURACY
No missing codes 18 bits
PSRR FIN = 1 MHz 50 dB
ADC3581: 10 MSPS
DNL Differential nonlinearity FIN = 5 MHz ± 0.7 ± 0.9 LSB
INL Integral nonlinearity FIN = 5 MHz ± 7 ± 16 LSB
VOS_ERR Offset error ± 10 ± 410 LSB
VOS_DRIFT Offset drift over temperature -0.01 LSB/ºC
GAINERR Gain error External 1.6V Reference 0.44 %FSR
GAINDRIFT Gain drift over temperature External 1.6V Reference 0.9 ppm/ºC
GAINERR Gain error Internal Reference -1.2 %FSR
GAINDRIFT Gain drift over temperature Internal Reference 88 ppm/ºC
Transition Noise 5 LSB
ADC3582: 25 MSPS
DNL Differential nonlinearity FIN = 5 MHz ± 0.7 ± 0.9 LSB
INL Integral nonlinearity FIN = 5 MHz ± 7 ± 16 LSB
VOS_ERR Offset error ± 40 ± 410 LSB
VOS_DRIFT Offset drift over temperature 0.03 LSB/ºC
GAINERR Gain error External 1.6V Reference -0.26 %FSR
GAINDRIFT Gain drift over temperature External 1.6V Reference 0.6 ppm/ºC
GAINERR Gain error Internal Reference -1.9 %FSR
GAINDRIFT Gain drift over temperature Internal Reference 85 ppm/ºC
Transition Noise 5 LSB
ADC3583: 65 MSPS
DNL Differential nonlinearity FIN = 5 MHz ± 0.7 ± 0.9 LSB
INL Integral nonlinearity FIN = 5 MHz ± 7 ± 19 LSB
VOS_ERR Offset error ± 130 ± 510 LSB
VOS_DRIFT Offset drift over temperature ± 0.2 LSB/ºC
GAINERR Gain error External 1.6V Reference ± 2.3 %FSR
GAINDRIFT Gain drift over temperature External 1.6V Reference 68 ppm/ºC
GAINERR Gain error Internal Reference ± 3.5 %FSR
GAINDRIFT Gain drift over temperature Internal Reference 242 ppm/ºC
Transition Noise 5 LSB
ADC ANALOG INPUT (AINP/M)
FS Input full scale Differential  3.2 Vpp
VCM Input common model voltage 0.9 0.95 1.0 V
RIN Differential input resistance FIN = 100 kHz 8 kΩ
CIN Differential input Capacitance FIN = 100 kHz 7 pF
VOCM Output common mode voltage 0.95 V
BW Analog Input Bandwidth (-3dB) 900 MHz
Internal Voltage Reference
VREF Internal reference voltage 1.6 V
VREF Output Impedance 8 Ω
Reference Input Buffer (REFBUF)
External reference voltage 1.2 V
External voltage reference (VREF)
VREF External voltage reference 1.6 V
Input Current 0.3 mA
Input impedance 5.3 kΩ
Clock Input (CLKP/M)
Input clock frequency 0.5 65 MHz
VID Differential input voltage 1 3.6 Vpp
VCM Input common mode voltage 0.9 V
RIN Single ended input resistance to common mode 5 kΩ
CIN Single ended input capacitance 1.5 pF
Clock duty cycle 40 50 60 %
Digital Inputs (RESET, PDN, SCLK, SEN, SDIO)
VIH High level input voltage 1.4 V
VIL Low level input voltage 0.4 V
IIH High level input current 90 150 uA
IIL Low level input current -150 -90 uA
CI Input capacitance 1.5 pF
Digital Output (SDOUT)
VOH High level output voltage ILOAD = -400 uA IOVDD – 0.1 IOVDD V
VOL Low level output voltage ILOAD = 400 uA 0.1 V
SLVDS Interface
Output data rate per differential SLVDS output pair 1000 Mbps
VID Differential input voltage DCLKIN 200 350 650 mVpp
VCM Input common mode voltage 1 1.2 1.3 V
VOD Differential output voltage 500 700 850 mVpp
VCM Output common mode voltage 1.0 V