JAJSL69A February   2021  – October 2022 ADC3581 , ADC3582 , ADC3583

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications
    8. 6.8  Timing Requirements
    9. 6.9  Typical Characteristics - ADC3581
    10. 6.10 Typical Characteristics - ADC3582
    11. 6.11 Typical Characteristics - ADC3583
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Bandwidth
        2. 8.3.1.2 Analog Front End Design
          1. 8.3.1.2.1 Sampling Glitch Filter Design
          2. 8.3.1.2.2 Analog Input Termination and DC Bias
            1. 8.3.1.2.2.1 AC-Coupling
            2. 8.3.1.2.2.2 DC-Coupling
        3. 8.3.1.3 Auto-Zero Feature
      2. 8.3.2 Clock Input
        1. 8.3.2.1 Single Ended vs Differential Clock Input
        2. 8.3.2.2 Signal Acquisition Time Adjust
      3. 8.3.3 Voltage Reference
        1. 8.3.3.1 Internal voltage reference
        2. 8.3.3.2 External voltage reference (VREF)
        3. 8.3.3.3 External voltage reference with internal buffer (REFBUF)
      4. 8.3.4 Digital Down Converter
        1. 8.3.4.1 DDC MUX for Dual Band Decimation
        2. 8.3.4.2 Digital Filter Operation
        3. 8.3.4.3 FS/4 Mixing with Real Output
        4. 8.3.4.4 Numerically Controlled Oscillator (NCO) and Digital Mixer
        5. 8.3.4.5 Decimation Filter
        6. 8.3.4.6 SYNC
        7. 8.3.4.7 Output Formatting with Decimation
      5. 8.3.5 Digital Interface
        1. 8.3.5.1 Output Formatter
        2. 8.3.5.2 Output Scrambler
        3. 8.3.5.3 Output Bit Mapper
        4. 8.3.5.4 Output Interface/Mode Configuration
          1. 8.3.5.4.1 Configuration Example
        5. 8.3.5.5 Output Data Format
      6. 8.3.6 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 Power Down Options
    5. 8.5 Programming
      1. 8.5.1 Configuration using PINs only
      2. 8.5.2 Configuration using the SPI interface
        1. 8.5.2.1 Register Write
        2. 8.5.2.2 Register Read
    6. 8.6 Register Map
      1. 8.6.1 Detailed Register Description
  9. 9 Application Information Disclaimer
    1. 9.1 Typical Application
      1. 9.1.1 Design Requirements
      2. 9.1.2 Detailed Design Procedure
        1. 9.1.2.1 Input Signal Path
        2. 9.1.2.2 Sampling Clock
        3. 9.1.2.3 Voltage Reference
      3. 9.1.3 Application Curves
    2. 9.2 Initialization Set Up
      1. 9.2.1 Register Initialization During Operation
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.8 Timing Requirements

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, 1.6 V external reference, and –1-dBFS differential input, unless otherwise noted
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
ADC Timing Specifications
tAD Aperture Delay 0.85 ns
tA Aperture Jitter Square wave clock with fast edges 180 fs
tJ Jitter on DCLKIN ± 50 ps
tACQ Signal acquisition period, referenced to sampling clock falling edge FS = 10 Msps -TS/2 Sampling Clock Period
FS = 25 Msps -TS/2
FS = 65 Msps -TS/4
tCONV Signal conversion period, referenced to sampling clock falling edge FS = 10 Msps +TS × 1/5 Sampling Clock Period
FS = 25 Msps +TS × 3/8
FS = 65 Msps +TS × 5/8
Wake up time Time to valid data after coming out of power down. Internal reference. Bandgap reference enabled, single ended clock 17.6 us
Bandgap reference enabled, differential clock 12.9
Bandgap reference disabled, single ended clock 2.2 ms
Bandgap reference disabled, differential clock 2.2
Time to valid data after coming out of power down.
External 1.6V reference.		 Bandgap reference enabled, single ended clock 15.9 us
Bandgap reference enabled, differential clock 12.9
Bandgap reference disabled, single ended clock 1.7 ms
Bandgap reference disabled, differential clock 1.7
tS,SYNC Setup time for SYNC input signal Referenced to sampling clock rising edge 500 ps
tH,SYNC Hold time for SYNC input signal 600
ADC Latency Signal input to data output SLVDS 2-wire 2 ADC clock cycles
SLVDS 1-wire 1
Add Latency Real decimation by 2 21   Output clock cycles
Complex decimation by 2   22  
Real or complex decimation by 4, 8, 16, 32   23  
Interface Timing: Serial LVDS Interface
tPD Propagation delay: sampling clock falling edge to DCLK rising edge Delay between sampling clock falling edge to DCLKIN falling edge < 2.5ns.
TDCLK = DCLK period
tCDCLK = Sampling clock falling edge to DCLKIN falling edge		 2 + TDCLK + tCDCLK 3 + TDCLK + tCDCLK 4 + TDCLK + tCDCLK ns
Delay between sampling clock falling edge to DCLKIN falling edge >= 2.5ns.
TDCLK = DCLK period
tCDCLK = Sampling clock falling edge to DCLKIN falling edge		 2 + tCDCLK 3 + tCDCLK 4 + tCDCLK ns
tCD DCLK rising edge to output data delay,
2-wire SLVDS		 Fout = 10 MSPS, DA/B0,1 = 90 MBPS 0 0.1 ns
Fout = 25 MSPS, DA/B0,1 = 225 MBPS 0 0.1
Fout = 65 MSPS, DA/B0,1 = 585 MBPS 0 0.1
DCLK rising edge to output data delay,
1-wire SLVDS		 Fout = 10 MSPS, DA/B0 = 180 MBPS 0.1 0.2
Fout = 25 MSPS, DA/B0 = 450 MBPS 0 0.1
Fout = 55 MSPS, DA/B0 = 990 MBPS -0.4 0.1
DCLK rising edge to output data delay,
1/2-wire SLVDS		 Fout = 5 MSPS, DA0 = 180 MBPS 0 0.1
Fout = 10 MSPS, DA0 = 360 MBPS 0 0.1
Fout = 25 MSPS, DA0 = 720 MBPS 0 0.1
tDV Data valid, 2-wire SLVDS Fout = 10 MSPS, DA/B0,1 = 90 MBPS 10.5 10.7 ns
Fout = 25 MSPS, DA/B0,1 = 225 MBPS 4.0 4.1
Fout = 65 MSPS, DA/B0,1 = 585 MBPS 1.3 1.4
Data valid, 1-wire SLVDS Fout = 10 MSPS, DA/B0 = 180 MBPS 4.7 4.8
Fout = 25 MSPS, DA/B0 = 450 MBPS 1.8 1.9
Fout = 55 MSPS, DA/B0 = 990 MBPS 0.5 0.6
Data valid, 1/2-wire SLVDS Fout = 5 MSPS, DA0 = 180 MBPS 4.7 4.8
Fout = 10 MSPS, DA0 = 360 MBPS 2.4 2.5
Fout = 25 MSPS, DA0 = 900 MBPS 0.6 0.7
SERIAL PROGRAMMING INTERFACE (SCLK, SEN, SDIO) - Input
fCLK(SCLK) Serial clock frequency 20 MHz
tSU(SEN) SEN to rising edge of SCLK 10 ns
tH(SEN) SEN from rising edge of SCLK 9 ns
tSU(SDIO) SDIO to rising edge of SCLK 17 ns
tH(SDIO) SDIO from rising edge of SCLK 9 ns
SERIAL PROGRAMMING INTERFACE (SDIO) - Output
t(OZD) SDIO tri-state to driven 3.9 10.8 ns
t(ODZ) SDIO data to tri-state 3.4 14 ns
t(OD) SDIO valid from falling edge of SCLK 3.9 10.8 ns