SBASAU8 December   2024 ADC3649

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications (ADC3648 - 250 MSPS)
    8. 6.8  Electrical Characteristics - AC Specifications (ADC3649 - 500 MSPS)
    9. 6.9  Timing Requirements
    10. 6.10 Typical Characteristics, ADC3648
    11. 6.11 Typical Characteristics, ADC3649
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Inputs
        1. 8.3.1.1 Nyquist Zone Selection
        2. 8.3.1.2 Analog Front End Design
      2. 8.3.2 Sampling Clock
      3. 8.3.3 Multi-Chip Synchronization
        1. 8.3.3.1 SYSREF Monitor
      4. 8.3.4 Time-Stamp
      5. 8.3.5 Overrange
      6. 8.3.6 External Voltage Reference
      7. 8.3.7 Digital Gain
      8. 8.3.8 Decimation Filter
        1. 8.3.8.1 Uncommon Decimation Ratios
        2. 8.3.8.2 Decimation Filter Response
        3. 8.3.8.3 Decimation Filter Configuration
        4. 8.3.8.4 Numerically Controlled Oscillator (NCO)
      9. 8.3.9 Digital Interface
        1. 8.3.9.1 Parallel LVDS
        2. 8.3.9.2 Serial LVDS (SLVDS) with Decimation
          1. 8.3.9.2.1 SLVDS - Status Bit Insertion
        3. 8.3.9.3 Output Data Format
        4. 8.3.9.4 32-bit Output Resolution
        5. 8.3.9.5 Output Scrambler
        6. 8.3.9.6 Output MUX
        7. 8.3.9.7 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low Latency Mode
      2. 8.4.2 Digital Channel Averaging
      3. 8.4.3 Power Down Mode
    5. 8.5 Programming
      1. 8.5.1 GPIO Programming
      2. 8.5.2 Register Write
      3. 8.5.3 Register Read
      4. 8.5.4 Device Programming
      5. 8.5.5 Register Map
      6. 8.5.6 Detailed Register Description
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Wideband Spectrum Analyzer
      2. 9.2.2 Design Requirements
        1. 9.2.2.1 Input Signal Path
        2. 9.2.2.2 Clocking
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Sampling Clock
      4. 9.2.4 Application Performance Plots
    3. 9.3 Initialization Set Up
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.4.2 Digital Channel Averaging

The device includes a digital channel averaging feature which enables improvement of the ADC dynamic range (see Figure 8-70). The same input signal is given to both ADC inputs externally and the output of the two ADCs is averaged internally. By averaging, uncorrelated noise (ADC thermal noise) improves 3dB while correlated noise (jitter in the clock path, reference noise) is unaffected. Therefore, the averaging gives close to 3dB improvement at low input frequencies but less at high input frequencies where clock jitter dominates the SNR. Using the DDC MUX select registers, the output from the digital averaging block is given out directly on the digital outputs of channel A or B or alternatively can be routed to the digital decimation filters.

ADC3649 Digital Channel Averaging DiagramFigure 8-70 Digital Channel Averaging Diagram

The digital averaging can be enabled with the following register writes:

Table 8-15 Example register write for 2x AVG output on channel A
ADDR DATA DESCRIPTION
0x162 0x04 Enable complex decimation
0x163 0x02 Configure <DDC0 MUX> to input from '2x Average output ((ChA + ChB) / 2)'
0x169 0x20 Set <NUM of DDCS> to 1 (single DDC mode) and <COMMON DECIMATION> TO 0 (DDC bypass)

Digital averaging improves decorrelated noise contributions by 3dB per 2x AVG while correlated noise does not improve with averaging. Some of the dominant noise sources are correlated like clock jitter (external or first clock input buffer) or power supply noise. While others (such as, ADC thermal noise, clock distribution buffers) are decorrelated. Figure 8-71 to Figure 8-74 show the FFT comparison of no vs 2x internal averaging.

SNR: When operating close to ADC fullscale, some of the SNR limitation is due to jitter and hence the SNR improvement does not reach 3dB (2x AVG). As the input fullscale is reduced, the clock jitter contribution to SNR becomes less and the SNR improvement is approaching the 3dB per 2x AVG. The same phenomenon can be observed when using digital decimation. As the decimation factor increases, the close-in (correlated noise) becomes the more dominating noise unless the input signal amplitude is reduced.

SFDR: The amplitude of low order harmonics (HD2-HD5) and IMD3 typically is similar across ADCs; thus, the improvement with averaging is small.

ADC3649 FFT - no AVG
SNR = 74.1dBFS FIN = 105MHz AIN = -1dBFS
Figure 8-71 FFT - no AVG
ADC3649 FFT - no AVG
SNR = 74.4dBFS FIN = 105MHz AIN = -20dBFS
Figure 8-73 FFT - no AVG
ADC3649 FFT - 2x AVG
SNR = 76.2dBFS FIN = 105MHz AIN = -1dBFS
Figure 8-72 FFT - 2x AVG
ADC3649 FFT - 2x AVG
SNR = 76.9dBFS FIN = 105MHz AIN = -20dBFS
Figure 8-74 FFT - 2x AVG