The SYSREF input signal rising edge must be edge aligned with the falling edge of the sampling clock to maximize the setup and hold times. The SYSREF signal is internally sampled on the rising edge of the sampling clock plus 60ps.

The device includes an internal SYSREF monitoring circuitry to detect a possible SYSREF logic level metastability close to the sampling instant of SYSREF which can lead to misalignment across devices. The SYSREF monitoring circuitry provides insights into SYSREF/clock misalignment by detecting whether a SYSREF logic state transition is within -60ps to +140ps of the sampling clock rising edge. This circuitry detects and raises one of the SYSREF XOR flags corresponding to the matching SYSREF window below:

• Window XOR1: SYSREF leading sample clock by 20 to 60ps
• Window XOR2: SYSREF leading sample clock by 20ps to 0ps or SYSREF lagging sample clock by 0 to 20ps
• Window XOR3: SYSREF lagging sample clock by up to 20 to 60ps
• Window XOR4: SYSREF lagging sample clock by 60 to 100ps
• Window XOR5: SYSREF lagging sample clock by 100 to 140ps

The SYSREF monitor registers are updated at every rising edge of SYSREF. The <SYSREF DET> register (D6) is sticky (indicating a SYSREF edge was detected) and needs to be cleared manually.

Figure 8-17 SYSREF Detection Circuitry

The example in Figure 8-18 shows a misaligned SYSREF signal where the SYSREF signal arrives much later than the sampling clock falling edge. In this example, the delayed SYSREF signal transitions between the "B" and "C" flip flop which raises the XOR2 flag. The XOR flags get reported in register 0x140. In this example, Register 0x140 reads back 0x62, as shown in Table 8-3.

Figure 8-18 Detection of SYSREF Transition Within Capture Window