SBASAU8 December   2024 ADC3649

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications (ADC3648 - 250 MSPS)
    8. 6.8  Electrical Characteristics - AC Specifications (ADC3649 - 500 MSPS)
    9. 6.9  Timing Requirements
    10. 6.10 Typical Characteristics, ADC3648
    11. 6.11 Typical Characteristics, ADC3649
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Inputs
        1. 8.3.1.1 Nyquist Zone Selection
        2. 8.3.1.2 Analog Front End Design
      2. 8.3.2 Sampling Clock
      3. 8.3.3 Multi-Chip Synchronization
        1. 8.3.3.1 SYSREF Monitor
      4. 8.3.4 Time-Stamp
      5. 8.3.5 Overrange
      6. 8.3.6 External Voltage Reference
      7. 8.3.7 Digital Gain
      8. 8.3.8 Decimation Filter
        1. 8.3.8.1 Uncommon Decimation Ratios
        2. 8.3.8.2 Decimation Filter Response
        3. 8.3.8.3 Decimation Filter Configuration
        4. 8.3.8.4 Numerically Controlled Oscillator (NCO)
      9. 8.3.9 Digital Interface
        1. 8.3.9.1 Parallel LVDS
        2. 8.3.9.2 Serial LVDS (SLVDS) with Decimation
          1. 8.3.9.2.1 SLVDS - Status Bit Insertion
        3. 8.3.9.3 Output Data Format
        4. 8.3.9.4 32-bit Output Resolution
        5. 8.3.9.5 Output Scrambler
        6. 8.3.9.6 Output MUX
        7. 8.3.9.7 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low Latency Mode
      2. 8.4.2 Digital Channel Averaging
      3. 8.4.3 Power Down Mode
    5. 8.5 Programming
      1. 8.5.1 GPIO Programming
      2. 8.5.2 Register Write
      3. 8.5.3 Register Read
      4. 8.5.4 Device Programming
      5. 8.5.5 Register Map
      6. 8.5.6 Detailed Register Description
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Wideband Spectrum Analyzer
      2. 9.2.2 Design Requirements
        1. 9.2.2.1 Input Signal Path
        2. 9.2.2.2 Clocking
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Sampling Clock
      4. 9.2.4 Application Performance Plots
    3. 9.3 Initialization Set Up
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

3 Description

The ADC3648 and ADC3649 (ADC364x) are a 14-bit, 250MSPS and 500MSPS, dual channel analog to digital converter (ADC). The devices are designed for high signal-to-noise ratio (SNR) and deliver a noise spectral density of -158.5dBFS/Hz (500MSPS).

The power efficient ADC architecture consumes 300mW/ch at 500MSPS and provides power scaling with lower sampling rates (250mW/ch at 250MSPS).

The ADC364x includes an optional quad band digital down-converter (DDC) supporting wide band decimation by 2 to narrow band decimation by 32768. The DDC uses a 48-bit NCO which supports phase coherent and phase continuous frequency hopping.

The ADC364x is outfitted with a flexible LVDS interface. In decimation bypass mode, the device uses a 14-bit wide parallel DDR LVDS interface. When using decimation, the output data is transmitted using a serial LVDS interface reducing the number of lanes needed as decimation increases. For high decimation rates, the output resolution can be increased to 32-bit.

Device Information
PART NUMBERPACKAGE(1)MAXIMUM SAMPLING RATE
ADC364964 VQFN500MSPS
ADC3648(2)64 VQFN250MSPS
(1) For more information, see Section 12.
(2) Product Preview


ADC3649 Block DiagramBlock Diagram