JAJSVH2 October   2024 ADC3908D025 , ADC3908D065 , ADC3908D125 , ADC3908S025 , ADC3908S065 , ADC3908S125

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications (25 MSPS)
    8. 6.8  Electrical Characteristics - AC Specifications (65 MSPS)
    9. 6.9  Electrical Characteristics - AC Specifications (125 MSPS)
    10. 6.10 Timing Requirements
    11. 6.11 Output Interface Timing Diagram
    12. 6.12 Typical Characteristics: 25MSPS
    13. 6.13 Typical Characteristics - 65MSPS
    14. 6.14 Typical Characteristics - 125MSPS
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
        1. 7.3.1.1 Single Ended Input
        2. 7.3.1.2 Differential Input
        3. 7.3.1.3 Analog Input Bandwidth
      2. 7.3.2 Sampling Clock Input
      3. 7.3.3 Digital Interface
        1. 7.3.3.1 Test Pattern
        2. 7.3.3.2 Interface Configuration using Pin Control
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Power Down
  9. 8 Application Information Disclaimer
    1. 8.1 Typical Application
      1. 8.1.1 Design Requirements
      2. 8.1.2 Detailed Design Procedure
        1. 8.1.2.1 Input Signal Path
        2. 8.1.2.2 Sampling Clock
      3. 8.1.3 Application Curves
    2. 8.2 Initialization Set Up
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.1.1 Design Requirements

Time domain applications cover a wide range of frequencies from low input frequencies at or near DC in the 1st Nyquist zone. If a low input frequency is supported, then the input has to be DC coupled and the ADC driven by a fully differential amplifier (FDA).

The ADC performance is highly dependent on the quality of the external clock source. A higher ADC sampling rate is desirable to relax the external anti-aliasing filter. For optimum performance, the analog inputs must be driven differentially.

Table 8-1 Design key care abouts
FEATURE DESCRIPTION
Signal Bandwidth DC to 30MHz
Input Driver Single ended to differential signal conversion and DC coupling
Clock Source External clock with low jitter

When designing the amplifier/filter driving circuit, the ADC input full-scale voltage needs to be taken into consideration. For example, the ADC3908D125 input full-scale is 1.9 VPP. When factoring in approximately 1dB for insertion loss of the filter, then the amplifier needs to deliver close to 2.1 VPP. The amplifier distortion performance degrades with a larger output swing and considering the ADC common mode input voltage the amplifier may not be able to deliver the full swing. The deviceADC3908D125 provides an output common mode voltage of 1.25V and the THS4541 for example can only swing within 250mV of its negative supply. A unipolar 3.3V amplifier power supply limits the maximum voltage swing to approximately 2.8VPP. Hence, if a larger output swing is required (factoring in filter insertion loss) then a negative supply for the amplifier is needed to eliminate that limitation. Additionally, input voltage protection diodes may be needed to protect the ADC from over-voltage events.

Table 8-2 Output voltage swing of THS4541 vs power supply
DEVICE MIN OUTPUT VOLTAGE MAX SWING WITH 3.3V/ 0V SUPPLY
THS4541 VS- + 250mV 2.8VPP