JAJSVH2 October   2024 ADC3908D025 , ADC3908D065 , ADC3908D125 , ADC3908S025 , ADC3908S065 , ADC3908S125

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications (25 MSPS)
    8. 6.8  Electrical Characteristics - AC Specifications (65 MSPS)
    9. 6.9  Electrical Characteristics - AC Specifications (125 MSPS)
    10. 6.10 Timing Requirements
    11. 6.11 Output Interface Timing Diagram
    12. 6.12 Typical Characteristics: 25MSPS
    13. 6.13 Typical Characteristics - 65MSPS
    14. 6.14 Typical Characteristics - 125MSPS
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
        1. 7.3.1.1 Single Ended Input
        2. 7.3.1.2 Differential Input
        3. 7.3.1.3 Analog Input Bandwidth
      2. 7.3.2 Sampling Clock Input
      3. 7.3.3 Digital Interface
        1. 7.3.3.1 Test Pattern
        2. 7.3.3.2 Interface Configuration using Pin Control
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Power Down
  9. 8 Application Information Disclaimer
    1. 8.1 Typical Application
      1. 8.1.1 Design Requirements
      2. 8.1.2 Detailed Design Procedure
        1. 8.1.2.1 Input Signal Path
        2. 8.1.2.2 Sampling Clock
      3. 8.1.3 Application Curves
    2. 8.2 Initialization Set Up
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.1 Overview

The ADC3908Dx および ADC3908Sx is a low noise, ultra-low power 8-bit high-speed single and dual channel ADC family supporting sampling rates up to 125MSPS. With the inherent low latency architecture, the digital output result is available after only one clock cycle. The ADC has buffered analog inputs which eases design by isolating the input from the ADC sampling operation. The ADC3908Dx および ADC3908Sx is equipped with an on-chip internal reference buffer and supports either single ended or differential input signaling.

The CMOS output data interface is configured as parallel DDR for dual channel devices and SDR for single channel devices with the option of 1.8V or 3.3V logic. The device supports 2's Complement or Offset Binary format options. The ADC3908Dx および ADC3908Sx offers DCLK as an alternate data clock for receivers that can not capture on the DCLK falling edge when using DDR interface. Table 7-1 shows the pin mapping to supply.

Table 7-1 Device Pin to Supply Mapping
Power Supply Device Pins
AVDD CLK, INxP|M, RESET, M0, M1, M2, PDN
IOVDD D0-D7, DCLK, DCLK