JAJSVH2 October 2024 ADC3908D025 , ADC3908D065 , ADC3908D125 , ADC3908S025 , ADC3908S065 , ADC3908S125
PRODUCTION DATA
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
INPUT or REFERENCE | |||
INAP | 10 | I | Positive analog input, channel A |
INAM | 11 | I | Negative analog input, channel A |
INBP/NC | 14 | I | Positive analog input, channel B (NC on single channel device) |
INBM/NC | 15 | I | Negative analog input, channel B (NC on single channel device) |
VCM | 7 | O | Common-mode voltage output for the analog inputs, 1.25 V |
CLOCK | |||
CLK | 8 | I | Sampling clock input for the ADC |
CONFIGURATION | |||
RESET | 9 | I | Hardware reset. Active high. This pin has an internal 60 kΩ pull-down resistor. |
M0 | 16 | I | Default, internal 40 kΩ
pull-down resistor. Tie to GND for dual channel devices or AVDD for single channel devices. This pin is used to configure default operating conditions. Interface configuration table |
M1 | 18 | I | Default, internal 40 kΩ pull-down resistor. This pin is used to configure default operating conditions. Interface configuration table |
M2 | 19 | I | Default, internal 40 kΩ pull-down resistor. This pin is used to configure default operating conditions. Interface configuration table |
DIGITAL INTERFACE | |||
D0 | 32 | O | Parallel CMOS digital lane output data. |
D1 | 31 | O | |
D2 | 26 | O | |
D3 | 25 | O | |
D4 | 24 | O | |
D5 | 23 | O | |
D6 | 22 | O | |
D7 | 21 | O | |
DCLK | 30 | O | CMOS output for data bit clock. |
DCLK | 29 | O | Inverse data bit clock for CMOS output data. |
PDN | 6 | I | Default, pin has 60 kΩ pull-down. When PDN is pulled high device is put in a powerdown state. |
POWER SUPPLY | |||
AVDD | 12, 13 | I | Analog 1.8 V power supply |
GND | PowerPAD™ | I | Analog Ground, 0 V |
IOVDD | 27 | I | 1.8 V power supply for digital interface |
DGND | 5, 28 | I | Ground, 0 V for digital interface |
OTHER | |||
NC | 1, 2, 3, 4, 5, 17, 20 | - | No connection. Connect to ground. |