JAJSVH2 October   2024 ADC3908D025 , ADC3908D065 , ADC3908D125 , ADC3908S025 , ADC3908S065 , ADC3908S125

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications (25 MSPS)
    8. 6.8  Electrical Characteristics - AC Specifications (65 MSPS)
    9. 6.9  Electrical Characteristics - AC Specifications (125 MSPS)
    10. 6.10 Timing Requirements
    11. 6.11 Output Interface Timing Diagram
    12. 6.12 Typical Characteristics: 25MSPS
    13. 6.13 Typical Characteristics - 65MSPS
    14. 6.14 Typical Characteristics - 125MSPS
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
        1. 7.3.1.1 Single Ended Input
        2. 7.3.1.2 Differential Input
        3. 7.3.1.3 Analog Input Bandwidth
      2. 7.3.2 Sampling Clock Input
      3. 7.3.3 Digital Interface
        1. 7.3.3.1 Test Pattern
        2. 7.3.3.2 Interface Configuration using Pin Control
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Power Down
  9. 8 Application Information Disclaimer
    1. 8.1 Typical Application
      1. 8.1.1 Design Requirements
      2. 8.1.2 Detailed Design Procedure
        1. 8.1.2.1 Input Signal Path
        2. 8.1.2.2 Sampling Clock
      3. 8.1.3 Application Curves
    2. 8.2 Initialization Set Up
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Electrical Characteristics - DC Specifications

Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages. Typical values are specified at TA = 25°C, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, Internal 1.2 V reference, and –1-dBFS differential input, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC ACCURACY (25 MSPS)
No missing codes 8 bits
DNL Differential nonlinearity -0.35 ±0.15 +0.35 LSB
INL Integral nonlinearity -0.6 ±0.25 +0.6 LSB
VOS_ERR Offset error -2.75 ±1 +2.75 LSB
VOS_DRIFT Offset drift over temperature 0.001 LSB/ºC
GAINERR Gain error Internal Reference ±0.8 %FSR
GAINDRIFT Gain drift over temperature Internal Reference -102 ppm/ºC
DC ACCURACY (65 MSPS)
No missing codes 8 bits
DNL Differential nonlinearity -0.35 ±0.15 +0.35 LSB
INL Integral nonlinearity -0.6 ±0.25 +0.6 LSB
VOS_ERR Offset error -2.75 ±1 -2.75 LSB
VOS_DRIFT Offset drift over temperature 0.001 LSB/ºC
GAINERR Gain error Internal Reference ±0.8 %FSR
GAINDRIFT Gain drift over temperature Internal Reference -102 ppm/ºC
DC ACCURACY (125 MSPS)
No missing codes 8 bits
DNL Differential nonlinearity -0.35 ±0.15 +0.35 LSB
INL Integral nonlinearity -0.6 ±0.25 +0.6 LSB
VOS_ERR Offset error -2.75 ±1 2.75 LSB
VOS_DRIFT Offset drift over temperature 0.001 LSB/ºC
GAINERR Gain error Internal Reference ±0.8 %FSR
GAINDRIFT Gain drift over temperature Internal Reference -102 ppm/ºC
ADC ANALOG INPUT (INAP/M, INBP/M)
FS Input full scale Differential 1.9 Vpp
Single-ended 0.95 Vpp
CIN Differential input Capacitance FIN = 100 kHz 7 pF
VCM Input common mode voltage VOCM - 50mV 1.275 VOCM + 50mV V
VOCM Output common mode voltage 1.25 V
BW Analog Input Bandwidth (-3dB) 150 MHz
CLOCK INPUT
Input clock frequency ADC3908D125, ADC3908S125 5 125 MHz
ADC3908D065, ADC3908S065 5 65 MHz
ADC3908D025, ADC3908S025 5 25 MHz
VIH High level input voltage AVDD - 0.3 1.8 Vpp
VIL Low level input voltage 0 AVSS + 0.3 V
CIN Input capacitance 0.5 pF
Clock duty cycle 45 50 55 %
DIGITAL INPUTS (RESET, PDN, M0, M1, M2)
VIH High level input voltage 1.4 V
VIL Low level input voltage 0.4 V
IIH High level input current 90 150 uA
IIL Low level input current -150 -90 uA
CI Input capacitance 1.5 pF
DIGITAL CMOS OUTPUTS (D0:D07)
Output data rate per CMOS output pin 250 Mbps
VOH High level output voltage ILOAD = -400 uA IOVDD - 0.1 IOVDD V
VOL Low level output voltage ILOAD = 400 uA 0.1 V