JAJSQJ8 January   2024 ADS1014L , ADS1015L

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Timing Requirements
    7. 6.7 Timing Diagram
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Multiplexer
      2. 7.3.2 Analog Inputs
      3. 7.3.3 Full-Scale Range (FSR) and LSB Size
      4. 7.3.4 Voltage Reference
      5. 7.3.5 Oscillator
      6. 7.3.6 Output Data Rate and Conversion Time
      7. 7.3.7 Digital Comparator
      8. 7.3.8 Conversion-Ready Pin
      9. 7.3.9 SMBus Alert Response
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset and Power-Up
      2. 7.4.2 Operating Modes
        1. 7.4.2.1 Single-Shot Mode
        2. 7.4.2.2 Continuous-Conversion Mode
    5. 7.5 Programming
      1. 7.5.1 I2C Interface
        1. 7.5.1.1 I2C Address Selection
        2. 7.5.1.2 I2C Interface Speed
          1. 7.5.1.2.1 Serial Clock (SCL) and Serial Data (SDA)
        3. 7.5.1.3 I2C Data Transfer Protocol
        4. 7.5.1.4 Timeout
        5. 7.5.1.5 I2C General-Call (Software Reset)
      2. 7.5.2 Reading and Writing Register Data
        1. 7.5.2.1 Reading Conversion Data or the Configuration Register
        2. 7.5.2.2 Writing the Configuration Register
      3. 7.5.3 Data Format
  9. Register Map
  10. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Basic Connections
      2. 9.1.2 Unused Inputs and Outputs
      3. 9.1.3 Single-Ended Inputs
      4. 9.1.4 Input Protection
      5. 9.1.5 Analog Input Filtering
      6. 9.1.6 Connecting Multiple Devices
      7. 9.1.7 Duty Cycling For Low Power
      8. 9.1.8 I2C Communication Sequence Example
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power-Supply Sequencing
      2. 9.3.2 Power-Supply Decoupling
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

I2C Communication Sequence Example

This section provides an example of an I2C communication sequence between a microcontroller (the controller) and a ADS101xL (the target) configured with a target address of 1001 000b to start a single-shot conversion and subsequently read the conversion result.

  1. Write the Configuration register as shown in Figure 9-6 to configure the device (for example, when using the ADS1015L, write MUX[2:0] = 000b, PGA[2:0] = 010b, MODE = 1b, and DR[2:0] = 110b) and start a single-shot conversion (OS = 1b).
    GUID-20230719-SS0I-7WFM-S5M9-3ZNBGZDTDVTK-low.svg Figure 9-5 Write the Configuration Register
  2. Wait at least t = 1 / DR ± 10% for the conversion to complete.

    Alternatively, poll the OS bit for a 1b as shown in Figure 9-6 to determine when the conversion result is ready for retrieval. This option does not work in continuous-conversion mode because the OS bit always reads 0b.

    GUID-20230719-SS0I-3DMX-603G-Z0FWV3BNSRSQ-low.svg Figure 9-6 Read the Configuration Register to Check for OS = 1b
  3. Then, as shown in Figure 9-7, read the Conversion register.
    GUID-20230719-SS0I-LJ0C-MPBQ-XZ0VVB7LLQG6-low.svg Figure 9-7 Read the Conversion Register
  4. Start a new single-shot conversion by writing a 1b to the OS bit in the Configuration register.

    To save time, a new conversion can also be started (step 4) before reading the conversion result (step 3). Figure 9-8 lists a legend for Figure 9-5 to Figure 9-7.

GUID-20230710-SS0I-DDMP-VZNM-PKBPR0RFC3QW-low.svg Figure 9-8 Legend for the I2C Sequence Diagrams