JAJSQJ8 January   2024 ADS1014L , ADS1015L

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Timing Requirements
    7. 6.7 Timing Diagram
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Multiplexer
      2. 7.3.2 Analog Inputs
      3. 7.3.3 Full-Scale Range (FSR) and LSB Size
      4. 7.3.4 Voltage Reference
      5. 7.3.5 Oscillator
      6. 7.3.6 Output Data Rate and Conversion Time
      7. 7.3.7 Digital Comparator
      8. 7.3.8 Conversion-Ready Pin
      9. 7.3.9 SMBus Alert Response
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset and Power-Up
      2. 7.4.2 Operating Modes
        1. 7.4.2.1 Single-Shot Mode
        2. 7.4.2.2 Continuous-Conversion Mode
    5. 7.5 Programming
      1. 7.5.1 I2C Interface
        1. 7.5.1.1 I2C Address Selection
        2. 7.5.1.2 I2C Interface Speed
          1. 7.5.1.2.1 Serial Clock (SCL) and Serial Data (SDA)
        3. 7.5.1.3 I2C Data Transfer Protocol
        4. 7.5.1.4 Timeout
        5. 7.5.1.5 I2C General-Call (Software Reset)
      2. 7.5.2 Reading and Writing Register Data
        1. 7.5.2.1 Reading Conversion Data or the Configuration Register
        2. 7.5.2.2 Writing the Configuration Register
      3. 7.5.3 Data Format
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Basic Connections
      2. 9.1.2 Unused Inputs and Outputs
      3. 9.1.3 Single-Ended Inputs
      4. 9.1.4 Input Protection
      5. 9.1.5 Analog Input Filtering
      6. 9.1.6 Connecting Multiple Devices
      7. 9.1.7 Duty Cycling For Low Power
      8. 9.1.8 I2C Communication Sequence Example
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power-Supply Sequencing
      2. 9.3.2 Power-Supply Decoupling
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 I2C Timing Requirements

over operating ambient temperature range, VDD = 2 V to 3.6 V, bus capacitance ≤ 400 pF, and pullup resistor = 1 kΩ (unless otherwise noted)
MIN MAX UNIT
STANDARD MODE
fSCL SCL clock frequency 0 100 kHz
tHD;STA Hold time, (repeated) START condition. After this period, the first clock pulse is generated. 4.0 µs
tLOW Pulse duration, SCL low 4.7 µs
tHIGH Pulse duration, SCL high 4.0 µs
tSU;STA Setup time, repeated START condition 4.7 µs
tHD;DAT Hold time, data 0 µs
tSU;DAT Setup time, data 0.25 µs
tr Rise time, SCL, SDA 1 µs
tf Fall time, SCL, SDA 0.3 µs
tSU;STO Setup time, STOP condition 4.0 µs
tBUF Bus free time, between STOP and START conditions 4.7 µs
tVD;DAT Valid time, data 3.45 µs
tVD;ACK Valid time, acknowledge 3.45 µs
FAST MODE
fSCL SCL clock frequency 0 400 kHz
tHD;STA Hold time, (repeated) START condition. After this period, the first clock pulse is generated. 600 ns
tLOW Pulse duration, SCL low 1300 ns
tHIGH Pulse duration, SCL high 600 ns
tSU;STA Setup time, repeated START condition 600 ns
tHD;DAT Hold time, data 0 ns
tSU;DAT Setup time, data 100 ns
tr Rise time, SCL, SDA 20 300 ns
tf Fall time, SCL, SDA 20 × (VDD / 5.5 V) 300 ns
tSU;STO Setup time, STOP condition 600 ns
tBUF Bus free time, between STOP and START conditions 1300 ns
tVD;DAT Valid time, data 900 ns
tVD;ACK Valid time, acknowledge 900 ns
tSP Pulse duration of spikes that must be suppressed by the input filter 0 50 ns