SBAS683B August 2014 – May 2020 ADS1120-Q1
PRODUCTION DATA.
To implement a ratiometric bridge measurement, the bridge excitation voltage is simultaneously used as the reference voltage for the ADC, as shown in Figure 82. With this configuration, any drift in excitation voltage also shows up on the reference voltage, consequently canceling out drift error. Either of the two device reference input pairs can be connected to the bridge excitation voltage. However, only the negative reference input (REFN1) can be internally routed to a low-side power switch. By connecting the low side of the bridge to REFN1, the device can automatically power-down the bridge by opening the low-side power switch. When the PSW bit in the configuration register is set to 1, the device opens the switch every time a POWERDOWN command is issued and closes the switch again when a START/SYNC command is sent.
The PGA offers gains up to 128, which helps amplify the small differential bridge output signal to make optimal use of the ADC full-scale range. Using a symmetrical bridge with the excitation voltage equal to the supply voltage of the device ensures that the output signal of the bridge meets the common-mode voltage requirement of the PGA.
Note that the maximum input voltage of ADS1120-Q1 is limited to VIN (MAX) = ±[(AVDD – AVSS) – 0.4 V] / Gain, which means the entire full-scale range, FSR = ±(AVDD – AVSS) / Gain, cannot be used in this configuration. This limitation is a result of the output drive capability of the PGA amplifiers (A1 and A2); see Figure 39. The output of each amplifier must stay 200 mV away from the rails (AVDD and AVSS), otherwise the PGA becomes nonlinear. Consequently, the maximum output swing of the PGA is limited to VOUT = ±[(AVDD – AVSS) – 0.4 V].
Using a 2-mV/V load cell with a 5-V excitation yields a maximum differential output voltage of VIN (MAX) = ±10 mV, which meets Equation 42 when using a gain of 128.
A first-order differential and common-mode RC filter (RF1, RF2, CDIF1, CCM1, and CCM2) is placed on the ADC inputs. The reference has an additional capacitor CDIF2 to limit reference noise. Care must be taken to maintain a limited amount of filtering or the measurement will no longer be ratiometric.
The device is capable of 16-bit, noise-free resolution using a gain of 128 at 20 SPS for the specified reference voltage. Accordingly the device is able to resolve signals as small as one LSB. The LSB size is calculated using Equation 43:
To find the total number of counts available for the bridge measurement, the maximum output voltage is divided by the LSB value. Dividing 10 mV by 1.192 µV equates to 8389 total counts available, which meets the design parameter of 8000 counts.
The register settings for this design are shown in Table 22.
REGISTER | SETTING | DESCRIPTION |
---|---|---|
00h | 3Eh | AINP = AIN1, AINN = AIN2, gain = 128, PGA enabled |
01h | 04h | DR = 20 SPS, normal mode, continuous-conversion mode |
02h | 98h | External reference (REFP1, REFN1), simultaneous 50-Hz and 60-Hz rejection, PSW = 1 |
03h | 00h | No IDACs used |