9.2.2.2 Detailed Design Procedure

The circuit in Figure 77 employs a ratiometric measurement approach. In other words, the sensor signal (that is, the voltage across the RTD in this case) and the reference voltage for the ADC are derived from the same excitation source. Therefore, errors resulting from temperature drift or noise of the excitation source cancel out because these errors are common to both the sensor signal and the reference.

In order to implement a ratiometric 3-wire RTD measurement using the device, IDAC1 is routed to one of the leads of the RTD and IDAC2 is routed to the second RTD lead. Both currents have the same value, which is programmable by the IDAC[2:0] bits in the configuration register. The design of the device ensures that both IDAC values are closely matched, even across temperature. The sum of both currents flows through a precision, low-drift reference resistor, R_REF. The voltage, V_REF, generated across the reference resistor (as shown in Equation 20) is used as the ADC reference voltage. Equation 20 reduces to Equation 21 because I_IDAC1 = I_IDAC2.

To simplify the following discussion, the individual lead resistance values of the RTD (R_LEADx) are set to zero. Only IDAC1 excites the RTD to produce a voltage (V_RTD) proportional to the temperature-dependable RTD value and the IDAC1 value, as shown in Equation 22.

The device internally amplifies the voltage across the RTD using the PGA and compares the resulting voltage against the reference voltage to produce a digital output code proportional to Equation 23 through Equation 25:

As can be seen from Equation 25, the output code only depends on the value of the RTD, the PGA gain, and the reference resistor (R_REF), but not on the IDAC1 value. The absolute accuracy and temperature drift of the excitation current therefore does not matter. However, because the value of the reference resistor directly affects the measurement result, choosing a reference resistor with a very low temperature coefficient is important to limit errors introduced by the temperature drift of R_REF.

The second IDAC2 is used to compensate for errors introduced by the voltage drop across the lead resistance of the RTD. All three leads of a 3-wire RTD typically have the same length and, thus, the same lead resistance. Also, IDAC1 and IDAC2 have the same value. Taking the lead resistance into account, the differential voltage (V_IN) across the ADC inputs, AIN0 and AIN1, is calculated using Equation 26:

When R_LEAD1 = R_LEAD2 and I_IDAC1 = I_IDAC2, Equation 26 reduces to Equation 27:

In other words, the measurement error resulting from the voltage drop across the RTD lead resistance is compensated, as long as the lead resistance values and the IDAC values are well matched.

A first-order differential and common-mode RC filter (R_F1, R_F2, C_DIF1, C_CM1, and C_CM2) is placed on the ADC inputs, as well as on the reference inputs (R_F3, R_F4, C_DIF2, C_CM3, and C_CM4). The same guidelines for designing the input filter apply as described in the Thermocouple Measurement section. For best performance, TI recommends matching the corner frequencies of the input and reference filter. More detailed information on matching the input and reference filter can be found in application report RTD Ratiometric Measurements and Filtering Using the ADS1148 and ADS1248 (SBAA201).

The reference resistor R_REF not only serves to generate the reference voltage for the device, but also sets the common-mode voltage of the RTD to within the specified common-mode voltage range of the PGA.

When designing the circuit, care must also be taken to meet the compliance voltage requirement of the IDACs. The IDACs require that the maximum voltage drop developed across the current path to AVSS be equal or less than AVDD – 0.9 V in order to operate accurately. This requirement means that Equation 28 must be met at all times.

The device also offers the possibility to route the IDACs to the same inputs used for measurement. If the filter resistor values R_F1 and R_F2 are small enough and well matched, IDAC1 can be routed to AIN1 and IDAC2 to AIN0 in Figure 77. In this manner, even two 3-wire RTDs sharing the same reference resistor can be measured with a single device.

This design example discusses the implementation of a 3-wire Pt100 measurement to be used to measure temperatures ranging from –200°C to +850°C as stated in Table 19. The excitation current for the Pt100 is chosen as I_IDAC1 = 500 µA, which means a combined current of 1 mA is flowing through the reference resistor, R_REF. As mentioned previously, besides creating the reference voltage for the ADS1120-Q1, the voltage across R_REF also sets the common-mode voltage for the RTD measurement. In general, choose the largest reference voltage possible while still maintaining the compliance voltage of the IDACs as well as meeting the common-mode voltage requirement of the PGA. TI recommends setting the common-mode voltage at or near half the analog supply (in this case 3.3 V / 2 = 1.65 V), which in most cases satisfies the common-mode voltage requirements of the PGA. The value for R_REF is then calculated by Equation 29:

The stability of R_REF is critical to achieve good measurement accuracy over temperature and time. Choosing a reference resistor with a temperature coefficient of ±10 ppm/°C or better is advisable. If a 1.65 kΩ value is not readily available, another value near 1.65 kΩ (such as 1.62 kΩ or 1.69 kΩ) can certainly be used as well.

As a last step, the PGA gain must be selected in order to match the maximum input signal to the FSR of the ADC. The resistance of a Pt100 increases with temperature. Therefore, the maximum voltage to be measured (V_{IN (MAX)}) occurs at the positive temperature extreme. At 850°C, a Pt100 has an equivalent resistance of approximately 391 Ω as per the NIST tables. The voltage across the Pt100 equates to Equation 30:

The maximum gain that can be applied when using a 1.65-V reference is then calculated as (1.65 V / 195.5 mV) = 8.4. The next smaller PGA gain setting available in the ADS1120-Q1 is 8. At a gain of 8, the ADS1120-Q1 offers a FSR value as described in Equation 31:

This range allows for margin with respect to initial accuracy and drift of the IDACs and reference resistor.

After selecting the values for the IDACs, R_REF, and PGA gain, make sure to double check that the settings meet the common-mode voltage requirements of the PGA and the compliance voltage of the IDACs. To determine the true common-mode voltage at the ADC inputs (AIN0 and AIN1) the lead resistance must be taken into account as well.

The smallest common-mode voltage occurs at the lowest measurement temperature (–200°C) with R_LEADx = 0 Ω and is calculated using Equation 32 and Equation 33.

Actually, assuming V_{CM (MIN)} = V_REF is a sufficient approximation.

V_{CM (MIN)} must meet two requirements: Equation 15 requires V_{CM (MIN)} to be larger than AVDD / 4 = 3.3 V / 4 = 0.825 V and Equation 13 requires V_{CM (MIN)} to meet Equation 34:

Both restrictions are satisfied in this design with a V_{CM (MIN)} = 1.65 V.

The largest common-mode voltage occurs at the highest measurement temperature (850°C) and is calculated using Equation 35 and Equation 36.

V_{CM (MAX)} does meet the requirement given by Equation 14, which in this design equates to Equation 37:

Finally, the maximum voltage that can occur on input AIN1 must be calculated to determine if the compliance voltage (AVDD – 0.9 V = 3.3 V – 0.9 V = 2.4 V) of IDAC1 is met. Note that the voltage on input AIN0 is smaller than the one on input AIN1. Equation 38 and Equation 39 show that the voltage on AIN1 is less than 2.4 V, even when taking the worst-case lead resistance into account.

The register settings for this design are shown in Table 20.