JAJSF20B October   2017  – October 2018 ADS122C04

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      Kタイプ熱電対温度の測定
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Timing Requirements
    7. 7.7 I2C Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Noise Performance
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Multiplexer
      2. 9.3.2  Low-Noise Programmable Gain Stage
        1. 9.3.2.1 PGA Input Voltage Requirements
        2. 9.3.2.2 Bypassing the PGA
      3. 9.3.3  Voltage Reference
      4. 9.3.4  Modulator and Internal Oscillator
      5. 9.3.5  Digital Filter
      6. 9.3.6  Conversion Times
      7. 9.3.7  Excitation Current Sources
      8. 9.3.8  Sensor Detection
      9. 9.3.9  System Monitor
      10. 9.3.10 Temperature Sensor
        1. 9.3.10.1 Converting From Temperature to Digital Codes
          1. 9.3.10.1.1 For Positive Temperatures (For Example, 50°C):
          2. 9.3.10.1.2 For Negative Temperatures (For Example, –25°C):
        2. 9.3.10.2 Converting From Digital Codes to Temperature
      11. 9.3.11 Offset Calibration
      12. 9.3.12 Conversion Data Counter
      13. 9.3.13 Data Integrity Features
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-Up and Reset
        1. 9.4.1.1 Power-On Reset
        2. 9.4.1.2 RESET Pin
        3. 9.4.1.3 Reset by Command
      2. 9.4.2 Conversion Modes
        1. 9.4.2.1 Single-Shot Conversion Mode
        2. 9.4.2.2 Continuous Conversion Mode
      3. 9.4.3 Operating Modes
        1. 9.4.3.1 Normal Mode
        2. 9.4.3.2 Turbo Mode
        3. 9.4.3.3 Power-Down Mode
    5. 9.5 Programming
      1. 9.5.1 I2C Interface
        1. 9.5.1.1 I2C Address
        2. 9.5.1.2 Serial Clock (SCL) and Serial Data (SDA)
        3. 9.5.1.3 Data Ready (DRDY)
        4. 9.5.1.4 Interface Speed
        5. 9.5.1.5 Data Transfer Protocol
        6. 9.5.1.6 I2C General Call (Software Reset)
        7. 9.5.1.7 Timeout
      2. 9.5.2 Data Format
      3. 9.5.3 Commands
        1. 9.5.3.1 Command Latching
        2. 9.5.3.2 RESET (0000 011x)
        3. 9.5.3.3 START/SYNC (0000 100x)
        4. 9.5.3.4 POWERDOWN (0000 001x)
        5. 9.5.3.5 RDATA (0001 xxxx)
        6. 9.5.3.6 RREG (0010 rrxx)
        7. 9.5.3.7 WREG (0100 rrxx dddd dddd)
      4. 9.5.4 Reading Data and Monitoring for New Conversion Results
      5. 9.5.5 Data Integrity
    6. 9.6 Register Map
      1. 9.6.1 Configuration Registers
      2. 9.6.2 Register Descriptions
        1. 9.6.2.1 Configuration Register 0 (address = 00h) [reset = 00h]
          1. Table 19. Configuration Register 0 Field Descriptions
        2. 9.6.2.2 Configuration Register 1 (address = 01h) [reset = 00h]
          1. Table 20. Configuration Register 1 Field Descriptions
        3. 9.6.2.3 Configuration Register 2 (address = 02h) [reset = 00h]
          1. Table 22. Configuration Register 2 Field Descriptions
        4. 9.6.2.4 Configuration Register 3 (address = 03h) [reset = 00h]
          1. Table 23. Configuration Register 3 Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Interface Connections
      2. 10.1.2 Connecting Multiple Devices on the Same I2C Bus
      3. 10.1.3 Unused Inputs and Outputs
      4. 10.1.4 Analog Input Filtering
      5. 10.1.5 External Reference and Ratiometric Measurements
      6. 10.1.6 Establishing Proper Limits on the Absolute Input Voltage
      7. 10.1.7 Pseudo Code Example
    2. 10.2 Typical Applications
      1. 10.2.1 K-Type Thermocouple Measurement (–200°C to +1250°C)
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 3-Wire RTD Measurement (–200°C to +850°C)
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Design Variations for 2-Wire and 4-Wire RTD Measurements
        3. 10.2.2.3 Application Curves
      3. 10.2.3 Resistive Bridge Measurement
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Sequencing
    2. 11.2 Power-Supply Decoupling
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all specifications are at AVDD = 2.3 V to 5.5 V, AVSS = 0 V, DVDD = 3.3 V, PGA enabled, all data rates, and internal reference enabled (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
Absolute input current PGA disabled, gain = 1 to 4, normal mode, VIN = 0 V ±5 nA
PGA disabled, gain = 1 to 4, turbo mode, VIN = 0 V ±10
Gain = 1 to 128, VIN = 0 V ±1
Absolute input current drift PGA disabled, gain = 1 to 4, VIN = 0 V 10 pA/°C
Gain = 1 to 128, VIN = 0 V 5
Differential input current PGA disabled, gain = 1 to 4, normal mode,
VCM = AVDD / 2, –VREF / Gain ≤ VIN ≤ VREF / Gain		 ±5 nA
PGA disabled, gain = 1 to 4, turbo mode,
VCM = AVDD / 2, –VREF / Gain ≤ VIN ≤ VREF / Gain		 ±10
Gain = 1 to 128,
VCM = AVDD / 2, –VREF / Gain ≤ VIN ≤ VREF / Gain		 ±1
Differential input current drift PGA disabled, gain = 1 to 4,
VCM = AVDD / 2, –VREF / Gain ≤ VIN ≤ VREF / Gain		 10 pA/°C
Gain = 1 to 128,
VCM = AVDD / 2, –VREF / Gain ≤ VIN ≤ VREF / Gain		 2
SYSTEM PERFORMANCE
Resolution (no missing codes) 24 Bits
DR Data rate Normal mode 20, 45, 90, 175, 330, 600, 1000 SPS
Turbo mode 40, 90, 180, 350, 660, 1200, 2000
Noise (input-referred)(1) Normal mode, gain = 128, DR = 20 SPS 110 nVRMS
INL Integral nonlinearity AVDD = 3.3 V, gain = 1 to 128, VCM = AVDD / 2, external VREF, normal mode, best fit –15 ±6 15 ppmFSR
VIO Input offset voltage PGA disabled, gain = 1 to 4, differential inputs ±4 µV
Gain = 1, differential inputs, TA = 25°C –150 ±5 150
Gain = 2 to 128, differential inputs ±4
Offset drift vs temperature PGA disabled, gain = 1 to 4 0.02 µV/°C
Gain = 1 to 128 0.1 0.6
Gain error(2) PGA disabled, gain = 1 to 4 ±0.01%
Gain = 1 to 32, TA = 25°C –0.05% ±0.01% 0.05%
Gain = 64 to 128, TA = 25°C –0.1% ±0.015% 0.1%
Gain drift vs temperature(2) PGA disabled, gain = 1 to 4 0.5 ppm/°C
Gain = 1 to 32 0.5 2
Gain = 64 to 128 1 4
SYSTEM PERFORMANCE (continued)
NMRR Normal-mode rejection ratio 50 Hz ±1 Hz, DR = 20 SPS 78 88 dB
60 Hz ±1 Hz, DR = 20 SPS 80 88
CMRR Common-mode rejection ratio At dc, gain = 1, AVDD = 3.3 V 90 105 dB
fCM = 50 Hz or 60 Hz, DR = 20 SPS, AVDD = 3.3 V 105 115
fCM = 50 Hz or 60 Hz, DR = 2 kSPS, AVDD = 3.3 V 95 110
PSRR Power-supply rejection ratio AVDD at dc, VCM = AVDD / 2 85 105 dB
DVDD at dc, VCM = AVDD / 2 95 115
INTERNAL VOLTAGE REFERENCE
VREF Reference voltage 2.048 V
Accuracy TA = 25°C, TSSOP package –0.15% ±0.01% 0.15%
TA = 25°C, WQFN package –0.25% ±0.04% 0.25%
Temperature drift 5 30 ppm/°C
Long-term drift 1000 hours 110 ppm
VOLTAGE REFERENCE INPUTS
Reference input current REFP = VREF, REFN = AVSS, AVDD = 3.3 V ±10 nA
INTERNAL OSCILLATOR
fCLK Frequency Normal mode 1.024 MHz
Turbo mode 2.048
Accuracy Normal mode –2% ±1% 2%
Turbo mode –4% ±2% 4%
EXCITATION CURRENT SOURCES (IDACs) (AVDD = 3.3 V to 5.5 V)
Current settings 10, 50, 100, 250, 500, 1000, 1500 µA
Compliance voltage All IDAC settings AVDD – 0.9 V
Accuracy (each IDAC) IDAC = 50 µA to 1.5 mA –6% ±1% 6%
Current matching between IDACs IDAC = 50 µA to 1.5 mA, TA = 25°C 0.3% 2%
Temperature drift (each IDAC) IDAC = 50 µA to 1.5 mA 50 ppm/°C
Temperature drift matching between IDACs IDAC = 50 µA to 1.5 mA 8 40 ppm/°C
BURN-OUT CURRENT SOURCES (BOCS)
Magnitude Sink and source 10 µA
Accuracy ±5%
TEMPERATURE SENSOR
Conversion resolution 14 Bits
Temperature resolution 0.03125 °C
Accuracy TA = 0°C to +85°C –1 ±0.25 1 °C
TA = –40°C to +125°C –1.5 ±0.5 1.5
Accuracy vs analog supply voltage 0.0625 0.25 °C/V
DIGITAL INPUTS/OUTPUTS
VIL Logic input level, low DGND 0.3 DVDD V
VIH Logic input level, high 2.3 V ≤ DVDD < 3.0 V,
SCL, SDA, A0, A1, DRDY 		0.7 DVDD DVDD + 0.5 V
3.0 V ≤ DVDD ≤ 5.5 V,
SCL, SDA, A0, A1, DRDY 		0.7 DVDD 5.5
RESET 0.7 DVDD DVDD
Vhys Hysteresis of Schmitt-trigger inputs Fast-mode, fast-mode plus 0.05 DVDD V
VOL Logic output level, low IOL = 3 mA DGND 0.15 0.4 V
IOL Low-level output current VOL = 0.4 V, standard-mode, fast-mode 3 mA
VOL = 0.4 V, fast-mode plus 20
VOL = 0.6 V, fast-mode 6
Ii Input current DGND + 0.1 V < VDigital Input < DVDD – 0.1 V –10 10 µA
Ci Capacitance Each pin 10 pF
ANALOG SUPPLY CURRENT (AVDD = 3.3 V, VIN = 0 V, IDACs Turned Off)
IAVDD Analog supply current Power-down mode 0.1 3 µA
Normal mode, PGA disabled, gain = 1 to 4 250
Normal mode, gain = 1 to 16 360 510
Normal mode, gain = 32 455
Normal mode, gain = 64, 128 550
Turbo mode, PGA disabled, gain = 1 to 4 370
Turbo mode, gain = 1 to 16 580
Turbo mode, gain = 32 765
Turbo mode, gain = 64, 128 955
ADDITIONAL ANALOG SUPPLY CURRENTS PER FUNCTION (AVDD = 3.3 V)
IAVDD Analog supply current External reference selected 60 µA
IDAC overhead (excludes the actual IDAC current) 195
DIGITAL SUPPLY CURRENT (DVDD = 3.3 V, All Data Rates, I2C Not Active)
IDVDD Digital supply current Power-down mode 0.3 5 µA
Normal mode 65 100
Turbo mode 100
POWER DISSIPATION (AVDD = DVDD = 3.3 V, All Data Rates, VIN = 0 V, I2C Not Active)
PD Power dissipation Normal mode, gain = 1 to 16 1.4 mW
Turbo mode, gain = 1 to 16 2.2
(1) See the Noise Performance section for more information.
(2) Excluding error of voltage reference.