JAJS168G June   2005  – January 2021 ADS1232 , ADS1234

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Performance
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Analog Inputs (AINPX, AINNX)
      2. 8.3.2  Temperature Sensor (ADS1232 Only)
      3. 8.3.3  Low-Noise PGA
        1. 8.3.3.1 PGA Bypass Capacitor
      4. 8.3.4  Voltage Reference Inputs (REFP, REFN)
      5. 8.3.5  Clock Sources
      6. 8.3.6  Digital Filter Frequency Response
      7. 8.3.7  Settling Time
      8. 8.3.8  Data Rate
      9. 8.3.9  Data Format
      10. 8.3.10 Data Ready and Data Output (DRDY/DOUT)
      11. 8.3.11 Serial Clock Input (SCLK)
      12. 8.3.12 Data Retrieval
    4. 8.4 Device Functional Modes
      1. 8.4.1 Offset Calibration Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Standby Mode With Offset-Calibration
      4. 8.4.4 Power-Down Mode
      5. 8.4.5 Power-Up Sequence
      6. 8.4.6 Summary of Serial Interface Waveforms
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.1 Noise Performance

The ADS123x offer outstanding noise performance that can be optimized for a given full-scale range using the programmable gain amplifier (PGA). Table 7-1 through Table 7-4 summarize the typical noise performance with inputs shorted externally for different gains, data rates, and voltage reference values. The RMS and peak-to-peak noise data are referred to the input.

The effective resolution of the ADC is defined as:

Equation 1. Effective Resolution (Bits) = ln (FSR / RMS Noise) / ln (2)

The noise-free resolution of the ADC is defined as:

Equation 2. Noise-Free Resolution (Bits)= ln (FSR / Peak-to-Peak Noise) / ln (2)

where

  • FSR = full-scale range = VREF / gain
Table 7-1 AVDD = 5 V, VREF = 5 V, Data Rate = 10 SPS
GAIN RMS NOISE PEAK-TO-PEAK NOISE(1) EFFECTIVE RESOLUTION (Bits) NOISE-FREE RESOLUTION (Bits)
1 420 nV 1.79 µV 23.5 21.4
2 270 nV 900 nV 23.1 21.4
64 19 nV 125 nV 22.0 19.2
128 17 nV 110 nV 21.1 18.4
(1) Peak-to-peak noise data are based on direct measurement.
Table 7-2 AVDD = 5 V, VREF = 5 V, Data Rate = 80 SPS
GAIN RMS NOISE PEAK-TO-PEAK NOISE(1) EFFECTIVE RESOLUTION (Bits) NOISE-FREE RESOLUTION (Bits)
1 1.36 µV 8.3 µV 21.8 19.2
2 850 nV 5.5 µV 21.5 18.8
64 48 nV 307 nV 20.6 18
128 44 nV 247 nV 19.7 17.2
(1) Peak-to-peak noise data are based on direct measurement.
Table 7-3 AVDD = 3 V, VREF = 3 V, Data Rate = 10 SPS
GAIN RMS NOISE PEAK-TO-PEAK NOISE(1) EFFECTIVE RESOLUTION (Bits) NOISE-FREE RESOLUTION (Bits)
1 450 nV 2.8 µV 22.6 20
2 325 nV 1.8 µV 22.1 19.7
64 20 nV 130 nV 21.2 18.5
128 18 nV 115 nV 20.3 17.6
(1) Peak-to-peak noise data are based on direct measurement.
Table 7-4 AVDD = 3 V, VREF = 3 V, Data Rate = 80 SPS
GAIN RMS NOISE PEAK-TO-PEAK NOISE(1) EFFECTIVE RESOLUTION (Bits) NOISE-FREE RESOLUTION (Bits)
1 2.2 µV 12 µV 20.4 17.9
2 1.2 µV 6.8 µV 20.2 17.8
64 54 nV 340 nV 19.7 17.1
128 48 nV 254 nV 18.9 16.5
(1) Peak-to-peak noise data are based on direct measurement of 1024 samples.