JAJS168G June   2005  – January 2021 ADS1232 , ADS1234

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Performance
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Analog Inputs (AINPX, AINNX)
      2. 8.3.2  Temperature Sensor (ADS1232 Only)
      3. 8.3.3  Low-Noise PGA
        1. 8.3.3.1 PGA Bypass Capacitor
      4. 8.3.4  Voltage Reference Inputs (REFP, REFN)
      5. 8.3.5  Clock Sources
      6. 8.3.6  Digital Filter Frequency Response
      7. 8.3.7  Settling Time
      8. 8.3.8  Data Rate
      9. 8.3.9  Data Format
      10. 8.3.10 Data Ready and Data Output (DRDY/DOUT)
      11. 8.3.11 Serial Clock Input (SCLK)
      12. 8.3.12 Data Retrieval
    4. 8.4 Device Functional Modes
      1. 8.4.1 Offset Calibration Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Standby Mode With Offset-Calibration
      4. 8.4.4 Power-Down Mode
      5. 8.4.5 Power-Up Sequence
      6. 8.4.6 Summary of Serial Interface Waveforms
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.3 Low-Noise PGA

The ADS123x feature a low-drift, low-noise PGA that provides a complete front-end solution for bridge sensors. A simplified diagram of the PGA is shown in Figure 8-2. The PGA consists of two chopper-stabilized amplifiers (A1 and A2) and three accurately matched resistors (R1, RF1, and RF2), which construct a differential front-end stage with a gain of 64, followed by gain stage A3. The PGA inputs are equipped with an EMI filter, as shown in Figure 8-2. The cut-off frequency of the EMI filter is 19.6 MHz. If the PGA gain is set to 1 or 2, the gain-of-64 stage is bypassed and shut down to save power. With the combination of both gain stages, the PGA gain can be set to 64 or 128. The PGA gain of the ADS123x is set to 1, 2, 64, or 128 by pins GAIN1 (MSB) and GAIN0 (LSB). Table 8-3 shows the gain setting of the PGA.

Table 8-3 PGA Gain
GAIN[1:0] INPUT PINS PGA GAIN
00 1
01 2
10 64
11 128

By using AVDD as the reference input, the bipolar input ranges from ±2.5 V to ±19.5 mV, while the unipolar ranges from 2.5 V to 19.5 mV. When the PGA gain is set to 1 or 2, the absolute inputs can go rail-to-rail without significant performance degradation. However, the inputs of the ADS123x are protected with internal diodes connected to the power-supply rails. These diodes clamp the applied signal to prevent damage to the input circuitry. On the other hand, when the PGA gain is set to 64 or 128, the operating input range is limited to (AGND + 1.5 V) to (AVDD – 1.5 V), in order to prevent saturating the differential front-end circuitry and degrading performance.

GUID-1B5C7BAC-7E7E-47B3-9A99-F3D76A3F6F73-low.gifFigure 8-2 Simplified Diagram of the PGA