JAJS168G June   2005  – January 2021 ADS1232 , ADS1234

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Performance
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Analog Inputs (AINPX, AINNX)
      2. 8.3.2  Temperature Sensor (ADS1232 Only)
      3. 8.3.3  Low-Noise PGA
        1. 8.3.3.1 PGA Bypass Capacitor
      4. 8.3.4  Voltage Reference Inputs (REFP, REFN)
      5. 8.3.5  Clock Sources
      6. 8.3.6  Digital Filter Frequency Response
      7. 8.3.7  Settling Time
      8. 8.3.8  Data Rate
      9. 8.3.9  Data Format
      10. 8.3.10 Data Ready and Data Output (DRDY/DOUT)
      11. 8.3.11 Serial Clock Input (SCLK)
      12. 8.3.12 Data Retrieval
    4. 8.4 Device Functional Modes
      1. 8.4.1 Offset Calibration Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Standby Mode With Offset-Calibration
      4. 8.4.4 Power-Down Mode
      5. 8.4.5 Power-Up Sequence
      6. 8.4.6 Summary of Serial Interface Waveforms
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.9 Data Format

The ADS123x output 24 bits of data in binary two’s complement format. The least significant bit (LSB) has a weight of 0.5 VREF / (223 – 1). The positive full-scale input produces an output code of 7FFFFFh and the negative full-scale input produces an output code of 800000h. The output clips at these codes for signals exceeding full-scale. Table 8-7 summarizes the ideal output codes for different input signals.

Table 8-7 Ideal Output Code Versus Input Signal(1)
INPUT SIGNAL VIN
(AINP – AINN)		 IDEAL OUTPUT CODE
≥ 0.5 VREF / Gain 7FFFFFh
(0.5 VREF / Gain) / (223 – 1) 000001h
0 000000h
(–0.5 VREF / Gain) / (223 – 1) FFFFFFh
≤ –0.5 VREF / Gain 800000h
(1) Excludes effects of noise, INL, offset, and gain errors.