JAJS168G June   2005  – January 2021 ADS1232 , ADS1234

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Performance
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Analog Inputs (AINPX, AINNX)
      2. 8.3.2  Temperature Sensor (ADS1232 Only)
      3. 8.3.3  Low-Noise PGA
        1. 8.3.3.1 PGA Bypass Capacitor
      4. 8.3.4  Voltage Reference Inputs (REFP, REFN)
      5. 8.3.5  Clock Sources
      6. 8.3.6  Digital Filter Frequency Response
      7. 8.3.7  Settling Time
      8. 8.3.8  Data Rate
      9. 8.3.9  Data Format
      10. 8.3.10 Data Ready and Data Output (DRDY/DOUT)
      11. 8.3.11 Serial Clock Input (SCLK)
      12. 8.3.12 Data Retrieval
    4. 8.4 Device Functional Modes
      1. 8.4.1 Offset Calibration Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Standby Mode With Offset-Calibration
      4. 8.4.4 Power-Down Mode
      5. 8.4.5 Power-Up Sequence
      6. 8.4.6 Summary of Serial Interface Waveforms
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.12 Data Retrieval

The ADS123x continuously converts the analog input signal. To retrieve data, wait until DRDY/DOUT goes low, as shown in Figure 8-9. After DRDY/DOUT goes low, begin shifting out the data by applying SCLKs. Data are shifted out MSB first. Not all 24 bits of data are required to be shifted out, but the data must be retrieved before new data are updated (within t7) or else the data are overwritten. Avoid data retrieval during the update period (t6). DRDY/DOUT remains at the state of the last bit shifted out until taken high (see t6), indicating that new data are being updated. To avoid having DRDY/DOUT remain in the state of the last bit, the user can shift SCLK to force DRDY/DOUT high, as shown in Figure 8-10. This technique is useful when a host controlling the device is polling DRDY/DOUT to determine when data are ready.

GUID-E3EAF9A8-71FC-4A77-A704-893A1D0817B9-low.gifFigure 8-9 Data Retrieval Timing
Table 8-8 Timing Requirements for Figure 8-9
PARAMETER MIN TYP MAX UNIT
t2 DRDY/DOUT low to first SCLK rising edge 0 ns
t3 SCLK positive or negative pulse width 100 ns
t4 SCLK rising edge to new data bit valid: propagation delay 50 ns
t5 SCLK rising edge to old data bit valid: hold time 0 ns
t6 (1) Data updating: no readback allowed 39 µs
t7 (1) Conversion time (1/data rate) SPEED = 1 12.5 ms
SPEED = 0 100
(1) Values given for fCLK = 4.9152 MHz. For different fCLK frequencies, scale proportional to the CLK period.
GUID-32A2182A-6A4D-47DA-AD36-8FDDC2DCF837-low.gifFigure 8-10 Data Retrieval With DRDY/DOUT Forced High Afterwards