JAJS168G June   2005  – January 2021 ADS1232 , ADS1234

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Performance
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Analog Inputs (AINPX, AINNX)
      2. 8.3.2  Temperature Sensor (ADS1232 Only)
      3. 8.3.3  Low-Noise PGA
        1. 8.3.3.1 PGA Bypass Capacitor
      4. 8.3.4  Voltage Reference Inputs (REFP, REFN)
      5. 8.3.5  Clock Sources
      6. 8.3.6  Digital Filter Frequency Response
      7. 8.3.7  Settling Time
      8. 8.3.8  Data Rate
      9. 8.3.9  Data Format
      10. 8.3.10 Data Ready and Data Output (DRDY/DOUT)
      11. 8.3.11 Serial Clock Input (SCLK)
      12. 8.3.12 Data Retrieval
    4. 8.4 Device Functional Modes
      1. 8.4.1 Offset Calibration Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Standby Mode With Offset-Calibration
      4. 8.4.4 Power-Down Mode
      5. 8.4.5 Power-Up Sequence
      6. 8.4.6 Summary of Serial Interface Waveforms
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.4.1 Offset Calibration Mode

Offset calibration can be initiated at any time to remove the ADS123x offset error. To initiate offset calibration, apply at least two additional SCLKs after retrieving 24 bits of data. Figure 8-11 shows the timing pattern. The 25th SCLK sends DRDY/DOUT high. The falling edge of the 26th SCLK begins the calibration cycle. Additional SCLK pulses can be sent after the 26th SCLK; however, minimize activity on SCLK during offset calibration for best results. The analog input pins are disconnected within the ADC and the appropriate signal is applied internally to perform the calibration.

When the calibration is completed, DRDY/DOUT goes low, indicating that new data are ready. The first conversion after a calibration is fully settled and valid for use. The offset calibration takes exactly the same time as specified in (t8) right after the falling edge of the 26th SCLK.

GUID-15A1332E-51C6-4BD6-B05D-C777DB431FE0-low.gifFigure 8-11 Offset-Calibration Timing
Table 8-9 Timing Requirements for Figure 8-11
PARAMETER MIN MAX UNIT
t8(1) First data ready after calibration SPEED = 1 (80 SPS) 101.28 101.29 ms
SPEED = 0 (10 SPS) 801.02 801.03
(1) Values given for fCLK = 4.9152 MHz. For different fCLK frequencies, scale proportional to the CLK period. Expect a ±3% variation when the internal oscillator is used.