JAJS168G June   2005  – January 2021 ADS1232 , ADS1234

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Performance
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Analog Inputs (AINPX, AINNX)
      2. 8.3.2  Temperature Sensor (ADS1232 Only)
      3. 8.3.3  Low-Noise PGA
        1. 8.3.3.1 PGA Bypass Capacitor
      4. 8.3.4  Voltage Reference Inputs (REFP, REFN)
      5. 8.3.5  Clock Sources
      6. 8.3.6  Digital Filter Frequency Response
      7. 8.3.7  Settling Time
      8. 8.3.8  Data Rate
      9. 8.3.9  Data Format
      10. 8.3.10 Data Ready and Data Output (DRDY/DOUT)
      11. 8.3.11 Serial Clock Input (SCLK)
      12. 8.3.12 Data Retrieval
    4. 8.4 Device Functional Modes
      1. 8.4.1 Offset Calibration Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Standby Mode With Offset-Calibration
      4. 8.4.4 Power-Down Mode
      5. 8.4.5 Power-Up Sequence
      6. 8.4.6 Summary of Serial Interface Waveforms
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.4.2 Standby Mode

Standby mode dramatically reduces power consumption by shutting down most of the circuitry. In standby mode, the entire analog circuitry is powered down and only the clock source circuitry is awake to reduce the wake-up time from the standby mode. To enter standby mode, simply hold SCLK high after DRDY/DOUT goes low; see Figure 8-12. Standby mode can be initiated at any time during readback; all 24 bits of data are not required to be retrieved beforehand.

When t10 has passed with SCLK held high, standby mode activates. DRDY/DOUT stays high when standby mode begins. SCLK must remain high to stay in standby mode. To exit standby mode (wakeup), set SCLK low. The first data after exiting standby mode is valid.

GUID-8AC284A9-100D-44DC-896D-A2C5A5F1BAED-low.gifFigure 8-12 Standby Mode Timing (Can be Used for Single Conversions)
Table 8-10 Timing Requirements for Figure 8-12
PARAMETER MIN MAX UNIT
t9(1) SCLK high after DRDY/DOUT goes low to activate standby mode SPEED = 1 0 12.44 ms
SPEED = 0 0 99.94
t10(1) Standby mode activation time SPEED = 1 12.46 ms
SPEED = 0 99.96
t11(1) Data ready after exiting standby mode SPEED = 1 52.51 52.51 ms
SPEED = 0 401.8 401.8
(1) Values given for fCLK = 4.9152 MHz. For different fCLK frequencies, scale proportional to the CLK period. Expect a ±3% variation when an internal oscillator is used.