JAJS168G June   2005  – January 2021 ADS1232 , ADS1234

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Noise Performance
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Analog Inputs (AINPX, AINNX)
      2. 8.3.2  Temperature Sensor (ADS1232 Only)
      3. 8.3.3  Low-Noise PGA
        1. 8.3.3.1 PGA Bypass Capacitor
      4. 8.3.4  Voltage Reference Inputs (REFP, REFN)
      5. 8.3.5  Clock Sources
      6. 8.3.6  Digital Filter Frequency Response
      7. 8.3.7  Settling Time
      8. 8.3.8  Data Rate
      9. 8.3.9  Data Format
      10. 8.3.10 Data Ready and Data Output (DRDY/DOUT)
      11. 8.3.11 Serial Clock Input (SCLK)
      12. 8.3.12 Data Retrieval
    4. 8.4 Device Functional Modes
      1. 8.4.1 Offset Calibration Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Standby Mode With Offset-Calibration
      4. 8.4.4 Power-Down Mode
      5. 8.4.5 Power-Up Sequence
      6. 8.4.6 Summary of Serial Interface Waveforms
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Clock Sources

The ADS123x can use an external clock source, external crystal, or internal oscillator to accommodate a wide variety of applications. Figure 8-4 shows the equivalent circuitry of the clock source. The CLK_DETECT block determines whether a crystal oscillator or external clock signal is applied to the CLKIN/XTAL1 pin so that the internal oscillator is bypassed or activated. When the CLKIN/XTAL1 pin frequency is above approximately 200 kHz, the CLK_DETECT output goes low and shuts down the internal oscillator. When the CLKIN/XTAL1 pin frequency is below approximately 200 kHz, the CLK_DETECT output goes high and activates the internal oscillator. Connect the CLKIN/XTAL1 pin to ground when the internal oscillator is chosen.

GUID-9342AEF3-FDFF-44C1-8E70-35F49CEF28D1-low.gifFigure 8-4 Equivalent Circuitry of the Clock Source

For crystal operation, connect the 4.9152-MHz crystal across the CLKIN/XTAL1 and XTAL2 pins. Table 8-4 shows the recommended crystal part numbers. As a result of the low-power design of the internal parallel-resonant circuit, both the CLKIN/XTAL1 and XTAL2 pins are only for use with the external crystal; do not use these pins as clock output drivers for external circuitry. No external capacitors are used with the crystal. Place the crystal as close as possible to the device pins in order to reduce board stray capacitance and in order to help ensure proper crystal operation.

Table 8-4 Recommended Crystals
MANUFACTURER FREQUENCY PART NUMBER
ECS 4.9152 MHz ECS-49-20-1
ECS 4.9152 MHz ECS-49-20-4

An external clock oscillator can be used by driving the CLKIN/XTAL1 pin from the oscillator output and leave XTAL2 disconnected.