For best performance, dedicate a PCB layer to a ground plane and do not route any other signal traces on this layer. However, depending on space limitations, a dedicated ground plane may not be practical. If a continuous ground plane is not possible, connect the individual plane segments in one place at the ADC.

Route digital traces away from the PGA output pins (CAP) and away from all analog inputs and associated components in order to minimize interference. Maintain differential trace routing for the input signal and reference signal to minimize RFI susceptibility.

Use C0G capacitors for analog and reference input filters and the PGA output capacitor in high-linearity applications. High-K type capacitors (such as Y5V and X7R) should be avoided. Place supply bypass and the PGA bypass capacitors as close as possible to the device pins using short, direct traces. For optimum performance, use low-impedance connections (such as multiple vias) on the ground-side connections of the bypass capacitors.

Avoid long traces on DRDY/DOUT, because high trace capacitance can lead to increased ADC noise. Use a series resistor or a local buffer if long traces are used. When applying an external clock, be sure the clock is free of overshoot and glitches. A source-termination resistor placed at the clock buffer helps control reflections and overshoot. Glitches present on the clock signal can lead to increased noise and possible mis-operation and must be avoided.

Figure 11-1 illustrates a PCB layout example. Separate 5-V analog and a 3.3-V digital supplies are shown. The ADC configuration is through hard-tie of the control pins as shown in Table 11-1.