JAJSHL9A June 2019 – January 2021 ADS125H01
PRODUCTION DATA
STATUS0 is shown in Figure 9-23 and described in Table 9-25.
Return to Register Map Summary.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | CRC1 | RESERVED | STAT12 | REFALM | DRDY | CLOCK | RESET |
| R/W-0h | R/W-0h | R/W-0h | R-0h | R-0h | R-0h | R-xh | R/W-1h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RESERVED | R/W | 0h | Reserved Always write 0. |
| 6 | CRC1 | R/W | 0h | CRC1 Error Indicates if a CRC error occurred during commands when CS1 is active. Write 0 to clear the CRC error. 0: No CRC error during commands using CS1 1: CRC error occurred during commands using CS1 See the STATUS2 register for the CRC error status for commands using CS2. |
| 5 | RESERVED | R/W | 0h | Reserved Always write 0. |
| 4 | STAT12 | R | 0h | STAT12 Error Flag Indicates one or more error events have been logged in the STATUS1 or STATUS2 registers. Read the STATUS1 and STATUS2 registers to determine the error. This bit clears automatically after all errors are cleared. 0: No error 1: Error logged in the STATUS1 or STATUS2 registers |
| 3 | REFALM | R | 0h | Reference Voltage Alarm This bit sets when the reference voltage falls below < 0.4 V (typical). The alarm updates at each new conversion cycle (auto-reset). 0: No reference low alarm 1: Reference low alarm |
| 2 | DRDY | R | 0h | Data Ready Indicates new conversion data. 0: Conversion data are not new from the last data read 1: Conversion data are new from the last data read |
| 1 | CLOCK | R | xh | Clock Indicates internal or external clock mode. The ADC automatically selects the clock mode. 0: ADC clock is internal 1: ADC clock is external |
| 0 | RESET | R/W | 1h | Reset Indicates an ADC reset has occurred. Clear the bit to detect the next device reset. 0: No reset 1: Reset (default) |