JAJSGW2A
January 2019 – May 2019
ADS1260-Q1
,
ADS1261-Q1
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
Device Images
ブロック図
4
改訂履歴
5
概要(続き)
6
Device Comparison Table
7
Pin Configuration and Functions
Pin Functions
8
Specifications
8.1
Absolute Maximum Ratings
8.2
ESD Ratings
8.3
Recommended Operating Conditions
8.4
Thermal Information
8.5
Electrical Characteristics
8.6
Timing Requirements
8.7
Switching Characteristics
9
Parameter Measurement Information
9.1
Noise Performance
10
Detailed Description
10.1
Overview
10.2
Functional Block Diagram
10.3
Feature Description
10.3.1
Analog Inputs
10.3.1.1
ESD Diodes
10.3.1.2
Input Multiplexer
10.3.1.3
Temperature Sensor
10.3.1.4
Power-Supply Readback
10.3.1.5
Inputs Open
10.3.1.6
Internal VCOM Connection
10.3.1.7
Alternate Functions
10.3.2
PGA
10.3.2.1
PGA Bypass Mode
10.3.2.2
PGA Voltage Monitor
10.3.3
Reference Voltage
10.3.3.1
Internal Reference
10.3.3.2
External Reference
10.3.3.3
AVDD - AVSS Reference (Default)
10.3.3.4
Reference Monitor
10.3.4
Level-Shift Voltage (VBIAS)
10.3.5
Burn-Out Current Sources
10.3.6
Sensor-Excitation Current Sources (IDAC1 and IDAC2)
10.3.7
General-Purpose Input/Outputs (GPIOs)
10.3.8
Oversampling
10.3.9
Modulator
10.3.10
Digital Filter
10.3.10.1
Sinc Filter
10.3.10.1.1
Sinc Filter Frequency Response
10.3.10.2
FIR Filter
10.3.10.2.1
FIR Filter Frequency Response
10.3.10.3
Filter Bandwidth
10.3.10.4
50-Hz and 60-Hz Normal Mode Rejection
10.4
Device Functional Modes
10.4.1
Conversion Control
10.4.1.1
Continuous-Conversion Mode
10.4.1.2
Pulse-Conversion Mode
10.4.1.3
Conversion Latency
10.4.1.4
Start-Conversion Delay
10.4.2
Chop Mode
10.4.3
AC-Excitation Mode
10.4.4
ADC Clock Mode
10.4.5
Power-Down Mode
10.4.5.1
Hardware Power-Down
10.4.5.2
Software Power-Down
10.4.6
Reset
10.4.6.1
Power-on Reset
10.4.6.2
Reset by Pin
10.4.6.3
Reset by Command
10.4.7
Calibration
10.4.7.1
Offset and Full-Scale Calibration
10.4.7.1.1
Offset Calibration Registers
10.4.7.1.2
Full-Scale Calibration Registers
10.4.7.2
Offset Self-Calibration (SFOCAL)
10.4.7.3
Offset System-Calibration (SYOCAL)
10.4.7.4
Full-Scale Calibration (GANCAL)
10.4.7.5
Calibration Command Procedure
10.4.7.6
User Calibration Procedure
10.5
Programming
10.5.1
Serial Interface
10.5.1.1
Chip Select (CS)
10.5.1.2
Serial Clock (SCLK)
10.5.1.3
Data Input (DIN)
10.5.1.4
Data Output/Data Ready (DOUT/DRDY)
10.5.1.5
Serial Interface Auto-Reset
10.5.2
Data Ready (DRDY)
10.5.2.1
DRDY in Continuous-Conversion Mode
10.5.2.2
DRDY in Pulse-Conversion Mode
10.5.2.3
Data Ready by Software Polling
10.5.3
Conversion Data
10.5.3.1
Status byte (STATUS)
10.5.3.2
Conversion Data Format
10.5.4
CRC
10.5.5
Commands
10.5.5.1
NOP Command
10.5.5.2
RESET Command
10.5.5.3
START Command
10.5.5.4
STOP Command
10.5.5.5
RDATA Command
10.5.5.6
SYOCAL Command
10.5.5.7
GANCAL Command
10.5.5.8
SFOCAL Command
10.5.5.9
RREG Command
10.5.5.10
WREG Command
10.5.5.11
LOCK Command
10.5.5.12
UNLOCK Command
10.6
Register Map
10.6.1
Device Identification (ID) Register (address = 00h) [reset = xxh]
Table 30.
ID Register Field Descriptions
10.6.2
Device Status (STATUS) Register (address = 01h) [reset = 01h]
Table 31.
STATUS Register Field Descriptions
10.6.3
Mode 0 (MODE0) Register (address = 02h) [reset = 24h]
Table 32.
MODE0 Register Field Descriptions
10.6.4
Mode 1 (MODE1) Register (address = 03h) [reset = 01h]
Table 33.
MODE1 Register Field Descriptions
10.6.5
Mode 2 (MODE2) Register (address = 04h) [reset = 00h]
Table 34.
MODE2 Register Field Descriptions
10.6.6
Mode 3 (MODE3) Register (address = 05h) [reset = 00h]
Table 35.
MODE3 Register Field Descriptions
10.6.7
Reference Configuration (REF) Register (address = 06h) [reset = 05h]
Table 36.
REF Register Field Descriptions
10.6.8
Offset Calibration (OFCALx) Registers (address = 07h, 08h, 09h) [reset = 00h, 00h, 00h]
Table 37.
OFCAL0, OFCAL1, OFCAL2 Registers Field Description
10.6.9
Full-Scale Calibration (FSCALx) Registers (address = 0Ah, 0Bh, 0Ch) [reset = 00h, 00h, 40h]
Table 38.
FSCAL0, FSCAL1, FSCAL2 Registers Field Description
10.6.10
IDAC Multiplexer (IMUX) Register (address = 0Dh) [reset = FFh]
Table 39.
IMUX Register Field Descriptions
10.6.11
IDAC Magnitude (IMAG) Register (address = 0Eh) [reset = 00h]
Table 40.
IMAG Register Field Descriptions
10.6.12
Reserved (RESERVED) Register (address = 0Fh) [reset = 00h]
Table 41.
RESERVED Register Field Descriptions
10.6.13
PGA Configuration (PGA) Register (address = 10h) [reset = 00h]
Table 42.
PGA Register Field Descriptions
10.6.14
Input Multiplexer (INPMUX) Register (address = 11h) [reset = FFh]
Table 43.
INPMUX Register Field Descriptions
10.6.15
Input Bias (INPBIAS) Register (address = 12h) [reset = 00h]
Table 44.
INPBIAS Register Field Descriptions
11
Application and Implementation
11.1
Application Information
11.1.1
Input Range
11.1.2
Input Overload
11.1.3
Burn-Out Current Source
11.1.4
Unused Inputs and Outputs
11.1.5
AC-Excitation
11.1.6
Serial Interface and Digital Connections
11.2
Typical Application
11.2.1
Design Requirements
11.2.2
Detailed Design Procedure
11.2.3
Application Curves
11.3
Initialization Setup
12
Power Supply Recommendations
12.1
Power-Supply Decoupling
12.2
Analog Power-Supply Clamp
12.3
Power-Supply Sequencing
13
Layout
13.1
Layout Guidelines
13.2
Layout Example
14
デバイスおよびドキュメントのサポート
14.1
ドキュメントのサポート
14.1.1
関連資料
14.2
関連リンク
14.3
ドキュメントの更新通知を受け取る方法
14.4
コミュニティ・リソース
14.5
商標
14.6
静電気放電に関する注意事項
14.7
Glossary
15
メカニカル、パッケージ、および注文情報
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RHM|32
MPQF152B
サーマルパッド・メカニカル・データ
RHM|32
QFND568
発注情報
jajsgw2a_oa
jajsgw2a_pm
10.5
Programming