JAJSF13C March 2018 – January 2019 ADS1260 , ADS1261
PRODUCTION DATA.
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IDAC1 current flows through reference resistor, RREF, which generates the ADC reference voltage, VREF = IIDAC1 · RREF. IDAC1 current also flows through the RTD element. Since the same current flows through RREF and the RTD element, the RTD measurement is ratiometric, which means the drift and error of the current source are cancelled. Therefore, the measurement accuracy is solely dependent on the tolerance of RREF and on ADC gain and offset errors. The errors are calibrated by host software control using shorted-input calibration and using a 400 Ω precision resistor for full-scale calibration.
The current of IDAC2 is programmed to the same value as IDAC1 and is connected to RLEAD2. IDAC2 generates an equal voltage drop across RLEAD1 and IDAC1. The accuracy of lead-wire compensation depends on the matching error between IDAC1 to IDAC2.
Using RRTD = 400 Ω, IDAC current = 500 µA, and gain = 8, the minimum ADC reference voltage requirement calculates to 1.6 V. To provide 10% design margin, RREF calculates to 3.52 kΩ (1.76 V / 500 µA). 500 µA is selected to minimize heating of the sensor.
Resistor RBIAS level-shifts the RTD voltage to meet the input range requirement of the ADC. This voltage is VRTDN and the low limit is calculated by Equation 8. The VRTDN low limit is 1 V.
Using 10% design margin, RBIAS calculates to 1.1 kΩ = 1.1 V / (2 · 500 µA). The next step is to verify the positive RTD voltage (VRTDP) does not exceed the maximum input range, as shown in Equation 9:
Evaluation of the equation results in the VRTDP high limit = 3.75 V. Calculate the actual VRTDP input voltage by Equation 10:
VRTDN = 1.1 V and VRTDP = 1.31 V satisfy the negative and positive input voltage requirements of the ADC, respectively.
Verify the burden voltage of current source IDAC1 is below the specified compliance range. The burden voltage is the sum of voltages in the IDAC1 loop as calculated by VRTDP+ (IDAC1 · RREF) + VD ( VD= external diode voltage). The result is 3.37 V, which meets the specified compliance voltage of the current source.
External filter components RF1, RF2, CDIF1, CCM1, CCM2) and RF3, RF4, CDIF2, CCM3, and CCM4) filter the signal and reference inputs of the ADC. The filters remove both differential and common-mode noise. The input signal differential filter cutoff frequency as calculated by Equation 11:
The Input signal common-mode filter is calculated by Equation 12:
Component mismatch in the common-mode filter converts common-mode noise into differential noise. Use a differential capacitor CDIF1 10× higher value than the common-mode capacitors, CCM1 and CCM2 to minimize the effects of mismatch. The recommended range of input resistors is 1 kΩ to 10 kΩ; increasing the resistance beyond 10 kΩ beyond can compromise noise and drift performance of the ADC. Use high-quality C0G ceramics or film-type capacitors. For consistent noise performance across the full RTD temperature range, match the corner frequencies of the input and reference filters. Detailed information is found in the RTD Ratiometric Measurements and Filtering Using the ADS1148 and ADS1248 Family of Devices application report.