JAJSG65B
September 2018 – December 2018
ADS1278-SP
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
Device Images
概略回路図
4
改訂履歴
5
概要(続き)
6
Pin Configuration and Functions
Pin Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Timing Requirements: SPI Format
7.7
Timing Requirements: Frame-Sync Format
7.8
Quality Conformance Inspection
7.9
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Sampling Aperture Matching
8.3.2
Frequency Response
8.3.2.1
High-Speed, Low-Power, And Low-Speed Modes
8.3.2.2
High-Resolution Mode
8.3.3
Phase Response
8.3.4
Settling Time
8.3.5
Data Format
8.3.6
Analog Inputs (AINP, AINN)
8.3.7
Voltage Reference Inputs (VREFP, VREFN)
8.3.8
Clock Input (CLK)
8.3.9
Mode Selection (MODE)
8.3.10
Synchronization (SYNC)
8.3.11
Power-Down (PWDN)
8.3.12
Format[2:0]
8.3.13
Serial Interface Protocols
8.3.14
SPI Serial Interface
8.3.14.1
SCLK
8.3.14.2
DRDY/FSYNC (SPI Format)
8.3.14.3
DOUT
8.3.14.4
DIN
8.3.15
Frame-Sync Serial Interface
8.3.15.1
SCLK
8.3.15.2
DRDY/FSYNC (Frame-Sync Format)
8.3.15.3
DOUT
8.3.15.4
DIN
8.3.16
DOUT Modes
8.3.16.1
TDM Mode
8.3.16.2
TDM Mode, Fixed-Position Data
8.3.16.3
TDM Mode, Dynamic Position Data
8.3.16.4
Discrete Data Output Mode
8.3.17
Daisy-Chaining
8.3.18
Modulator Output
8.3.19
Pin Test Using Test[1:0] Inputs
8.3.20
VCOM Output
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.3
Application Curve
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
デバイスおよびドキュメントのサポート
12.1
ドキュメントの更新通知を受け取る方法
12.2
コミュニティ・リソース
12.3
商標
12.4
静電気放電に関する注意事項
12.5
Glossary
13
メカニカル、パッケージ、および注文情報
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
HFQ|84
MCQF017A
サーマルパッド・メカニカル・データ
発注情報
jajsg65b_oa
8.2
Functional Block Diagram