The ADS127L01 is a 24-bit, delta-sigma (ΔΣ), analog-to-digital converter (ADC) with data rates up to 512 kSPS. This device offers a unique combination of excellent dc accuracy and outstanding ac performance. The high-order, chopper-stabilized modulator achieves very low drift with low in-band noise. The integrated decimation filter suppresses modulator out-of-band noise. In addition to al low-latency filter, the ADS127L01 provides multiple Wideband filters with less than ±0.00004 dB of ripple, and an option for –116-dB stop-band attenuation at the Nyquist rate.
Traditionally, industrial delta-sigma ADCs that offer good drift performance use digital filters with large passband droop. As a result, industrial delta-sigma ADCs have limited signal bandwidth and are mostly suited for dc measurements. High-resolution ADCs in audio applications offer larger usable bandwidths, but the offset and drift specifications are significantly weaker than industrial counterparts. The ADS127L01 combines these converters, providing high-precision industrial measurement with excellent dc and ac specifications over an extended industrial temperature range of –40°C to +125°C.
A variety of operating modes allow for optimization of speed, resolution, and power. A programmable serial interface with one of three options (SPI, frame-sync slave, or frame-sync master) provides convenient interfacing across isolation barriers to microcontrollers or digital signal processors (DSPs).
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
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ADS127L01 | TQFP (32) | 5.00 mm × 5.00 mm |
Changes from A Revision (May 2016) to B Revision
Changes from * Revision (April 2016) to A Revision
PIN | I/O | DESCRIPTION(3) | |||
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NO. | NAME | ||||
1 | LVDD | Supply | LVDD analog supply. INTLDO = 0: LVDD is an analog-supply output pin. Connect a 1-µF capacitor to AGND. INTLDO = 1: LVDD is an analog-supply input pin. Connect to a 1.8-V supply. |
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2 | CAP1 | Analog output | Modulator common-mode voltage. Connect a 1-µF capacitor to AGND |
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3 | AINN | Analog input | Negative analog input. | ||
4 | AINP | Analog input | Positive analog input. | ||
5 | AGND | Supply | Analog ground. | ||
6 | AVDD | Supply | Analog supply. Connect a 1-μF capacitor to AGND. |
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7 | REXT | Analog input | Analog power-scaling bias resistor pin. Recommended external resistor values: REXT = 60.4 kΩ to AGND for high-resolution (HR) and low-power (LP) modes REXT = 120 kΩ to AGND for very-low-power (VLP) mode |
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8 | INTLDO | Digital input | LVDD voltage selection pin (pull high to AVDD or low to AGND through 10-kΩ resistor). 0: Internal analog low-dropout regulator (LDO) for LVDD voltage supply. 1: External LVDD voltage supply. |
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9 | REFP | Analog input | Positive analog reference input. Connect a minimum 10-μF capacitor to REFN |
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10 | REFN | Analog input | Negative analog reference input. | ||
11 | CAP2 | Analog output | Reference common-mode voltage. Connect a 1-µF capacitor to AGND. |
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12 | FILTER1 | Digital input | Digital filter select pin(1). 00: Wideband 1 filter (WB1) 01: Wideband 2 filter (WB2) 10: Low-latency filter (LL) 11: Reserved |
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13 | FILTER0 | Digital input | |||
14 | FSMODE | Digital input | Frame-sync mode pin(1). 0: Slave mode 1: Master mode. Applies to Frame-Sync interface mode only. No effect in SPI interface mode. |
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15 | OSR1 | Digital input | Oversampling ratio (OSR) pin for the decimation filters(1). Wideband filters, FILTER[1:0] = 00 or 01: 00: 32x oversampling (OSR 32) 01: 64x oversampling (OSR 64) 10: 128x oversampling (OSR 128) 11: 256x oversampling (OSR 256) Low-latency filter, FILTER[1:0] = 10: 00: 32x oversampling (OSR 32) 01: 128x oversampling (OSR 128) 10: 512x oversampling (OSR 512) 11: 2048x oversampling (OSR 2048) |
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16 | OSR0 | Digital input | |||
17 | START | Digital input | Synchronization signal to start or restart a conversion. | ||
18 | DAISYIN | Digital input | Daisy-chain input. | ||
19 | DRDY/FSYNC | Digital input/output | SPI interface: Data ready, active low(2). Frame-sync interface: Frame-sync input signal(2) |
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20 | DOUT | Digital output | Serial data output | ||
21 | DIN | Digital input | Serial data input. Tie directly to DGND when using the frame-sync interface. |
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22 | SCLK | Digital input/output | Serial clock input(2). | ||
23 | CS | Digital input | Chip select. Tie directly to DGND when using the frame-sync interface. |
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24 | CLK | Digital input | Master clock input. | ||
25 | CAP3 | Analog output | Internally-generated digital operating voltage. Connect a 1-µF capacitor to DGND. |
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26 | DGND | Supply | Digital ground. | ||
27 | DVDD | Supply | Digital supply. Connect a 1-μF capacitor to DGND(2) |
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28 | RESET/PWDN | Digital input | Reset or power-down pin, active low(2). | ||
29 | HR | Digital input | ADC operating mode(1). 1: High-resolution (HR) 0: Low-power (LP) or very-low-power (VLP)(4) |
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30 | FORMAT | Digital input | Interface select pin(1). 0: SPI 1: Frame-Sync |
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31 | AGND | Supply | Analog ground. | ||
32 | AVDD | Supply | Analog supply. Decouple AVDD to AGND with a 1-μF capacitor. |