The ADS127L01 is a 24-bit, delta-sigma (ΔΣ), analog-to-digital converter (ADC) with data rates up to 512 kSPS. This device offers a unique combination of excellent dc accuracy and outstanding ac performance. The high-order, chopper-stabilized modulator achieves very low drift with low in-band noise. The integrated decimation filter suppresses modulator out-of-band noise. In addition to al low-latency filter, the ADS127L01 provides multiple Wideband filters with less than ±0.00004 dB of ripple, and an option for –116-dB stop-band attenuation at the Nyquist rate.
Traditionally, industrial delta-sigma ADCs that offer good drift performance use digital filters with large passband droop. As a result, industrial delta-sigma ADCs have limited signal bandwidth and are mostly suited for dc measurements. High-resolution ADCs in audio applications offer larger usable bandwidths, but the offset and drift specifications are significantly weaker than industrial counterparts. The ADS127L01 combines these converters, providing high-precision industrial measurement with excellent dc and ac specifications over an extended industrial temperature range of –40°C to +125°C.
A variety of operating modes allow for optimization of speed, resolution, and power. A programmable serial interface with one of three options (SPI, frame-sync slave, or frame-sync master) provides convenient interfacing across isolation barriers to microcontrollers or digital signal processors (DSPs).
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
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ADS127L01 | TQFP (32) | 5.00 mm × 5.00 mm |
Changes from A Revision (May 2016) to B Revision
Changes from * Revision (April 2016) to A Revision
PIN | I/O | DESCRIPTION(3) | |||
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NO. | NAME | ||||
1 | LVDD | Supply | LVDD analog supply. INTLDO = 0: LVDD is an analog-supply output pin. Connect a 1-µF capacitor to AGND. INTLDO = 1: LVDD is an analog-supply input pin. Connect to a 1.8-V supply. |
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2 | CAP1 | Analog output | Modulator common-mode voltage. Connect a 1-µF capacitor to AGND |
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3 | AINN | Analog input | Negative analog input. | ||
4 | AINP | Analog input | Positive analog input. | ||
5 | AGND | Supply | Analog ground. | ||
6 | AVDD | Supply | Analog supply. Connect a 1-μF capacitor to AGND. |
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7 | REXT | Analog input | Analog power-scaling bias resistor pin. Recommended external resistor values: REXT = 60.4 kΩ to AGND for high-resolution (HR) and low-power (LP) modes REXT = 120 kΩ to AGND for very-low-power (VLP) mode |
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8 | INTLDO | Digital input | LVDD voltage selection pin (pull high to AVDD or low to AGND through 10-kΩ resistor). 0: Internal analog low-dropout regulator (LDO) for LVDD voltage supply. 1: External LVDD voltage supply. |
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9 | REFP | Analog input | Positive analog reference input. Connect a minimum 10-μF capacitor to REFN |
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10 | REFN | Analog input | Negative analog reference input. | ||
11 | CAP2 | Analog output | Reference common-mode voltage. Connect a 1-µF capacitor to AGND. |
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12 | FILTER1 | Digital input | Digital filter select pin(1). 00: Wideband 1 filter (WB1) 01: Wideband 2 filter (WB2) 10: Low-latency filter (LL) 11: Reserved |
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13 | FILTER0 | Digital input | |||
14 | FSMODE | Digital input | Frame-sync mode pin(1). 0: Slave mode 1: Master mode. Applies to Frame-Sync interface mode only. No effect in SPI interface mode. |
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15 | OSR1 | Digital input | Oversampling ratio (OSR) pin for the decimation filters(1). Wideband filters, FILTER[1:0] = 00 or 01: 00: 32x oversampling (OSR 32) 01: 64x oversampling (OSR 64) 10: 128x oversampling (OSR 128) 11: 256x oversampling (OSR 256) Low-latency filter, FILTER[1:0] = 10: 00: 32x oversampling (OSR 32) 01: 128x oversampling (OSR 128) 10: 512x oversampling (OSR 512) 11: 2048x oversampling (OSR 2048) |
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16 | OSR0 | Digital input | |||
17 | START | Digital input | Synchronization signal to start or restart a conversion. | ||
18 | DAISYIN | Digital input | Daisy-chain input. | ||
19 | DRDY/FSYNC | Digital input/output | SPI interface: Data ready, active low(2). Frame-sync interface: Frame-sync input signal(2) |
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20 | DOUT | Digital output | Serial data output | ||
21 | DIN | Digital input | Serial data input. Tie directly to DGND when using the frame-sync interface. |
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22 | SCLK | Digital input/output | Serial clock input(2). | ||
23 | CS | Digital input | Chip select. Tie directly to DGND when using the frame-sync interface. |
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24 | CLK | Digital input | Master clock input. | ||
25 | CAP3 | Analog output | Internally-generated digital operating voltage. Connect a 1-µF capacitor to DGND. |
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26 | DGND | Supply | Digital ground. | ||
27 | DVDD | Supply | Digital supply. Connect a 1-μF capacitor to DGND(2) |
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28 | RESET/PWDN | Digital input | Reset or power-down pin, active low(2). | ||
29 | HR | Digital input | ADC operating mode(1). 1: High-resolution (HR) 0: Low-power (LP) or very-low-power (VLP)(4) |
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30 | FORMAT | Digital input | Interface select pin(1). 0: SPI 1: Frame-Sync |
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31 | AGND | Supply | Analog ground. | ||
32 | AVDD | Supply | Analog supply. Decouple AVDD to AGND with a 1-μF capacitor. |
MIN | MAX | UNIT | ||
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Voltage | AVDD to AGND | –0.3 | 4.0 | V |
DVDD to DGND | –0.3 | 4.0 | ||
LVDD to AGND | –0.3 | 2.0 | ||
AGND to DGND | –0.3 | 0.3 | ||
REFP to AGND | –0.3 | AVDD + 0.3 | ||
REFN to AGND | –0.3 | AVDD + 0.3 | ||
Analog input | AGND – 0.3 | AVDD + 0.3 | ||
Digital input | DGND – 0.3 | DVDD + 0.3 | ||
Current | Input, continuous, any pin except power supply pins (2) | –10 | 10 | mA |
Temperature | Operating ambient, TA | –40 | 125 | °C |
Junction, TJ | 150 | |||
Storage, Tstg | –60 | 150 |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
POWER SUPPLY | ||||||
AVDD | Analog power supply | 2.7 | 3.0 | 3.6 | V | |
LVDD | Low voltage analog supply | INTLDO = 1 | 1.7 | 1.8 | 1.9 | V |
DVDD | Digital supply | 1.7 | 1.8 | 3.6 | V | |
ANALOG INPUTS | ||||||
VIN | Differential input voltage | VIN = (VAINP – VAINN) | –VREF | VREF | V | |
VAINP, VAINN | Absolute input voltage | AINP or AINN to AGND | AGND | AVDD | V | |
VCM | Common-mode input voltage | VCM = (VAINP + VAINN) / 2 | AVDD / 2 | V | ||
VOLTAGE REFERENCE INPUTS | ||||||
VREFN | Negative reference input | AGND – 0.1 | AGND | AGND + 1.0 | V | |
VREFP | Positive reference input | VREFN + 0.5 | 2.5 | AVDD | V | |
VREF | Reference input voltage | VREF = VREFP – VREFN | 0.5 | 2.5 | 3.0 | V |
EXTERNAL CLOCK SOURCE | ||||||
fCLK | Master clock rate(1) | HR mode | 0.1 | 16.384 | 17.6 | MHz |
LP mode | 0.1 | 8.192 | 8.8 | |||
VLP mode | 0.1 | 4.096 | 4.4 | |||
DIGITAL INPUTS | ||||||
Input voltage | DGND | DVDD | V | |||
TEMPERATURE RANGE | ||||||
TA | Operating ambient temperature | –40 | 125 | °C |
THERMAL METRIC(1) | ADS127L01 | UNIT | |
---|---|---|---|
PBS (TQFP) | |||
32 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 73.4 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 15.9 | °C/W |
RθJB | Junction-to-board thermal resistance | 26.7 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.4 | °C/W |
ψJB | Junction-to-board characterization parameter | 26.5 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
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ANALOG INPUTS | ||||||||
Differential input impedance | HR mode, fCLK = 16.384 MHz | 5 | kΩ | |||||
LP mode, fCLK = 8.192 MHz | 11 | |||||||
VLP mode, fCLK = 4.096 MHz | 23 | |||||||
DC PERFORMANCE | ||||||||
Resolution | No missing codes | 24 | Bits | |||||
fDATA | Data rate | HR mode | Wideband filters | 512, 256, 128, 64 | kSPS | |||
Low-latency filter | 512, 128, 32, 8 | |||||||
LP mode | Wideband filters | 256, 128, 64, 32 | ||||||
Low-latency filter | 256, 64, 16, 4 | |||||||
VLP mode | Wideband filters | 128, 64, 32, 16 | ||||||
Low-latency filter | 128, 32, 8, 2 | |||||||
INL | Integral nonlinearity(1) | HR mode | VCM = AVDD / 2 | 2.5 | 10 | ppm | ||
LP mode | VCM = AVDD / 2 | 1 | 5 | |||||
VLP mode | VCM = AVDD / 2 | 1 | 5 | |||||
Offset error | ±0.1 | mV | ||||||
Offset drift | 1.5 | 3.0 | μV/°C | |||||
Gain error | 0.2 | %FSR | ||||||
Gain calibration accuracy | 0.003% | |||||||
Gain drift | HR mode | 0.8 | 3 | ppm/°C | ||||
LP mode | 0.4 | 2.5 | ||||||
VLP mode | 0.2 | 2 | ||||||
Noise(2) | HR mode | WB2, OSR 32 | 10.6 | μVRMS | ||||
WB2, OSR 64 | 7.3 | 10.1 | ||||||
WB2, OSR 128 | 5.1 | 7.2 | ||||||
WB2, OSR 256 | 3.6 | 5.2 | ||||||
CMRR | Common-mode rejection ratio | fCM = 60 Hz | 95 | dB | ||||
PSRR | Power-supply rejection ratio | fPS = 60 Hz | AVDD | 90 | dB | |||
DVDD | 85 | |||||||
LVDD | 80 | |||||||
AC PERFORMANCE | ||||||||
SNR | Signal-to-noise ratio(2)(3) | WB2, OSR 32 | 104.4 | dB | ||||
WB2, OSR 64 | 104.9 | 107.8 | ||||||
WB2, OSR 128 | 107.9 | 110.9 | ||||||
WB2, OSR 256 | 110.6 | 113.9 | ||||||
WB2, OSR 32, VREF = 3 V | 105.8 | |||||||
WB2, OSR 64, VREF = 3 V | 109.3 | |||||||
WB2, OSR 128, VREF = 3 V | 112 | |||||||
WB2, OSR 256, VREF = 3 V | 115.5 | |||||||
THD | Total harmonic distortion(4) | HR mode, fIN = 4 kHz, VIN = –0.5 dBFS | –113 | dB | ||||
LP mode, fIN = 4 kHz, VIN = –0.5 dBFS | –126 | |||||||
VLP mode, fIN = 4 kHz, VIN = –0.5 dBFS | –129 | |||||||
SFDR | Spurious-free dynamic range | HR mode | –115 | dB | ||||
LP mode | –130 | |||||||
VLP mode | –130 | |||||||
DIGITAL FILTER RESPONSE: WIDEBAND | ||||||||
Bandwidth | See Table 1 | |||||||
Pass-band ripple | ±0.000032 | dB | ||||||
Transition band | FILTER[1:0] = 00 (WB1) | (0.45 to 0.55) × fDATA | Hz | |||||
FILTER[1:0] = 01 (WB2) | (0.40 to 0.50) × fDATA | |||||||
Stop-band attenuation | 116 | dB | ||||||
Group delay | 42 / fDATA | s | ||||||
Settling time | Complete settling | 84 / fDATA | s | |||||
DIGITAL FILTER RESPONSE: LOW-LATENCY | ||||||||
Bandwidth | See Table 2 | |||||||
Group delay | See Low-Latency Filter section | |||||||
Settling time | See Low-Latency Filter section | |||||||
VOLTAGE REFERENCE INPUTS | ||||||||
Reference input impedance | HR mode | 2.2 | kΩ | |||||
LP mode | 3.2 | |||||||
VLP mode | 4 | |||||||
SYSTEM MONITORS | ||||||||
Input over-range detect accuracy | ±100 | mV | ||||||
DIGITAL INPUT/OUTPUT (DVDD = 1.7 V to 3.6 V) | ||||||||
VIH | High-level input voltage | 0.7 DVDD | DVDD | V | ||||
VIL | Low-level input voltage | DGND | 0.3 DVDD | V | ||||
VOH | High-level output voltage | IOH = 2 mA | 0.8 DVDD | DVDD | V | |||
VOL | Low-level output voltage | IOL = 2 mA | DGND | 0.2 DVDD | V | |||
IH | Input leakage, high | IH = 3.6 V | –10 | 10 | μA | |||
IL | Input leakage, low | IL = DGND | –10 | 10 | μA | |||
POWER SUPPLY | ||||||||
Power-down current | AVDD | INTLDO = 0 | 8 | μA | ||||
INTLDO = 1 | 2 | |||||||
DVDD | 0.6 | |||||||
LVDD, INTLDO = 1 | 0.6 | |||||||
IAVDD | AVDD current | HR mode | 1.3 | 1.6 | mA | |||
LP mode | 0.8 | 1.0 | ||||||
VLP mode | 0.4 | 0.6 | ||||||
ILVDD | LVDD current(5) (6) | HR mode | 9.3 | 11 | mA | |||
LP mode | 4.6 | 5.5 | ||||||
VLP mode | 2.3 | 2.8 | ||||||
IDVDD | DVDD current(2) | HR mode | OSR 128 | 2.8 | 3.4 | mA | ||
LP mode | OSR 128 | 1.5 | 1.8 | |||||
VLP mode | OSR 128 | 0.8 | 1.1 | |||||
PD | Power dissipation | HR mode, OSR 128, AVDD = 3.0 V, DVDD = 1.8 V |
INTLDO = 1, LVDD = 1.8 V, |
25.7 | 30.8 | mW | ||
INTLDO = 0 | 36.8 | 44.2 | ||||||
LP mode, OSR 128, AVDD = 3.0 V, DVDD = 1.8 V |
INTLDO = 1, LVDD = 1.8 V, |
13.4 | 16.1 | |||||
INTLDO = 0 | 18.9 | 22.7 | ||||||
VLP mode, OSR 128, AVDD = 3.0 V, DVDD = 1.8 V |
INTLDO = 1, LVDD = 1.8 V, |
6.8 | 8.2 | |||||
INTLDO = 0 | 9.5 | 11.4 |
2.8 V < DVDD ≤ 3.6 V | 1.7 V ≤ DVDD ≤ 2.8 V | UNIT | |||||||
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MIN | TYP | MAX | MIN | TYP | MAX | ||||
tc(CLK) | Master clock period | HR mode | 57 | 10,000 | 57 | 10,000 | ns | ||
LP mode | 114 | 10,000 | 114 | 10,000 | |||||
VLP mode | 227 | 10,000 | 227 | 10,000 | |||||
tw(CP) | Pulse duration, Master clock high or low | HR mode | 28 | 5,000 | 28 | 5,000 | ns | ||
LP mode | 56 | 5,000 | 56 | 5,000 | |||||
VLP mode | 112 | 5,000 | 112 | 5,000 | |||||
td(CSSC) | Delay time, CS falling edge to first SCLK rising edge(1) | 8 | 12 | ns | |||||
tc(SC) | SCLK period | 40 | 6250 | 50 | 6250 | ns | |||
tw(SCHL) | Pulse duration, SCLK high or low | 20 | 25 | ns | |||||
tsu(DI) | Setup time, DIN valid before SCLK falling edge | 6 | 9 | ns | |||||
th(DI) | Hold time, DIN valid after SCLK falling edge | 8 | 9 | ns | |||||
tw(CSH) | Pulse duration, CS high | 6 | 6 | tCLK | |||||
td(SCCS) | Delay time, final SCLK falling edge to CS rising edge | 2 | 2 | tCLK | |||||
td(DECODE) | Delay time, command decode time | 4 | 4 | tCLK | |||||
SPI timeout(2) | TOUT_DEL = 0 | 216 | 216 | tCLK | |||||
TOUT_DEL = 1 | 214 | 214 | tCLK | ||||||
tsu(DCI) | Setup time, DAISYIN valid before SCLK falling edge | 5 | 8 | ns | |||||
th(DCI) | Hold time, DAISYIN valid after SCLK falling edge | 20 | 25 | ns |
2.8 V < DVDD ≤ 3.6 V | 1.7 V ≤ DVDD ≤ 2.8 V | UNIT | |||||||
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MIN | TYP | MAX | MIN | TYP | MAX | ||||
tp(CSDO) | Propagation delay time, CS falling edge to DOUT driven |
12 | 18 | ns | |||||
tp(SCDO) | Propagation delay time, SCLK rising edge to valid new DOUT |
15 | 21 | ns | |||||
tv(DO) | Valid time, SCLK falling edge to DOUT invalid | 18 | tSCLK / 2 | 20 | tSCLK / 2 | ns | |||
tp(CSDOZ) | Propagation delay time, CS rising edge to DOUT high impedance |
20 | 20 | ns |
NOINDENT:
NOTE: SPI settings are CPOL = 0 and CPHA = 1.1.7 V ≤ DVDD ≤ 3.6 V | UNIT | |||||
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MIN | TYP | MAX | ||||
tc(CLK) | Master clock period | HR mode | 57 | 10,000 | ns | |
LP mode | 114 | 10,000 | ||||
VLP mode | 227 | 10,000 | ||||
tw(CP) | Pulse duration, Master clock high or low | HR mode | 28 | 5,000 | ns | |
LP mode | 56 | 5,000 | ||||
VLP mode | 112 | 5,000 |
2.8 V < DVDD ≤ 3.6 V | 1.7 V ≤ DVDD ≤ 2.8 V | UNIT | |||||||
---|---|---|---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | ||||
td(CSC) | Delay time, CLK rising edge to SCLK falling edge | 15 | 15 | ns | |||||
tc(FRAME) | Frame period | 1 / fDATA | 1 / fDATA | s | |||||
tw(FP) | Pulse duration, FSYNC high or low | 1 / (2fDATA) | 1 / (2fDATA) | s | |||||
td(FSSC) | Delay time, FSYNC rising edge to SCLK falling edge | 6 | 8 | ns | |||||
tc(SC) | SCLK period | 1 / (32fDATA) | 1 / (32fDATA) | s | |||||
tw(SCHL) | Pulse duration, SCLK high or low | 1 / (64fDATA) | 1 / (64fDATA) | s | |||||
tv(DO) | Valid time, SCLK rising edge to DOUT invalid | 25 | 25 | ns | |||||
tp(SCDO) | Propagation delay time, SCLK falling edge to DOUT driven |
15 | 17 | ns | |||||
tp(FSDO) | Propagation delay time, FSYNC rising edge to DOUT MSB valid |
12 | 15 | ns |
2.8 V < DVDD ≤ 3.6 V | 1.7 V ≤ DVDD ≤ 2.8 V | UNIT | |||||||
---|---|---|---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | ||||
tc(CLK) | Master clock period | HR mode | 57 | 10,000 | 57 | 10,000 | ns | ||
LP mode | 114 | 10,000 | 114 | 10,000 | |||||
VLP mode | 227 | 10,000 | 227 | 10,000 | |||||
tw(CP) | Pulse duration, Master clock high or low | HR mode | 28 | 5,000 | 28 | 5,000 | ns | ||
LP mode | 56 | 5,000 | 56 | 5,000 | |||||
VLP mode | 112 | 5,000 | 112 | 5,000 | |||||
td(CSC) | Delay time, CLK rising edge to SCLK falling edge | 2 | 2 | ns | |||||
tc(FRAME) | Frame period | 1 / fDATA | 1 / fDATA | s | |||||
tw(FP) | Pulse durration, FSYNC high or low | 2 | 2 | tSCLK | |||||
td(FSSC) | Delay time, FSYNC rising edge to SCLK falling edge | 6 | 6 | ns | |||||
td(SCFS) | Delay time, SCLK falling edge to FSYNC rising edge | 2 | 2 | ns | |||||
tc(SC) | SCLK period | 40 | 56 | ns | |||||
tw(SCHL) | Pulse duration, SCLK high or low | 20 | 28 | ns | |||||
DAISY-CHAIN TIMING | |||||||||
tsu(DCI) | Setup time, DAISYIN valid before SCLK rising edge | 8 | 8 | ns | |||||
th(DCI) | Hold time, DAISYIN valid after SCLK rising edge | 25 | 31 | ns |
2.8 V < DVDD ≤ 3.6 V | 1.7 V ≤ DVDD ≤ 2.8 V | UNIT | |||||||
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MIN | TYP | MAX | MIN | TYP | MAX | ||||
tv(DO) | Valid time, SCLK rising edge to DOUT invalid | 17 | 25 | ns | |||||
tp(SCDO) | Propagation delay time, SCLK falling edge to valid new DOUT |
22 | 22 | ns | |||||
tp(FSDO) | Propagation delay time, FSYNC rising edge to DOUT MSB valid |
15 | 22 | 25 | 32 | ns |
fIN = 4 kHz, VIN = –0.5 dBFS, HR mode, WB1, 512 kSPS, 32768 samples |
fIN = 4 kHz, VIN = –0.5 dBFS, LP mode, WB2, 256 kSPS, 32768 samples |
fIN = 4 kHz, VIN = –0.5 dBFS, VLP mode, WB2, 128 kSPS, 32768 samples |
Inputs shorted, HR mode, WB2, 512 kSPS, 32768 samples |
Inputs shorted, VLP mode, WB2, 128 kSPS, 32768 samples |
Inputs shorted, HR mode, 65536 points |
Inputs shorted |
WB2, OSR 32 |
HR mode, fIN = 4 kHz, VIN = –0.5 dBFS |
HR mode, fIN = 4 kHz, VIN = –0.5 dBFS |
VLP mode, fIN = 4 kHz, VIN = –0.5 dBFS |
HR mode, 30 Devices |
VLP mode, 30 Devices |
Inputs shorted, HR mode |
HR mode, INTLDO = 1 |
INTLDO = 1, LVDD = 1.8 V |
Inputs shorted, HR mode, LL, 512 kSPS, 32768 samples |
Inputs shorted, HR mode, LL, 32 kSPS, 32768 samples |
Inputs shorted, HR mode, LL, 512 kSPS, 32768 samples |
Inputs shorted, HR mode, LL, 32 kSPS, 32768 samples |
fIN = 4 kHz, VIN = –20 dBFS, HR mode, WB2, 512 kSPS, 32768 samples |
fIN = 4 kHz, VIN = –20 dBFS, HR mode, WB1, 512 kSPS, 32768 samples |
fIN = 4 kHz, VIN = –20 dBFS, LP mode, WB2, 256 kSPS, 32768 samples |
fIN = 4 kHz, VIN = –20 dBFS, VLP mode, WB2, 128 kSPS, 32768 samples |
Inputs shorted, LP mode, WB2, 256 kSPS, 32768 samples |
HR mode, 0.5 seconds data collection space |
Inputs shorted, HR mode |
Inputs shorted, HR mode |
WB2, OSR 32 |
fIN = 4 kHz, HR mode |
LP mode, fIN = 4 kHz, VIN = –0.5 dBFS |
Inputs shorted |
Inputs shorted |
Inputs shorted, 30 devices |
LP mode, 30 Devices |
HR mode |
HR mode, fCLK = 16.384 MHz |
HR mode, INTLDO = 0 |
INTLDO = 0 |
Inputs shorted, HR mode, LL, 128 kSPS, 32768 samples |
Inputs shorted, HR mode, LL, 8 kSPS, 32768 samples |
Inputs shorted, HR mode, LL, 128 kSPS, 32768 samples |
Inputs shorted, HR mode, LL, 8 kSPS, 32768 samples |
Adjust the oversampling ratio (OSR) to control the data rate and change the digital filter in order to optimize the noise performance of the ADS127L01. Hardware control pins offer four oversampling options and three selectable digital filter options to configure the ADC for a specific bandwidth of interest. When averaging is increased by reducing the data rate (increasing the OSR), the in-band noise drops as more samples from the modulator are averaged to yield one conversion result. Table 1 and Table 2 summarize the device noise performance across the various oversampling and digital filter options. Wideband 1 filter has a filter transition band of (0.45 to 0.55) fDATA, and Wideband 2 filter has a filter transition band of (0.40 to 0.50) fDATA. Data are representative of typical noise performance at TA = 25°C with an external 2.5-V reference. Data shown are the result of one standard deviation of the readings with the inputs shorted together and biased to midsupply. A minimum of 1,000 consecutive readings are used to calculate the VRMS_noise voltage noise for each measurement. Equation 1 is used to convert the noise in VRMS_noise to SNR, and Equation 2 is used to convert the noise in VRMS_noise to ENOB. The peak-to-peak noise for the Low-latency filter is defined as VPP_noise.