9.1.2.1 Cascaded Configuration

Two or more ADS127L01 devices can be cascaded together when using either SPI interface mode or Frame-Sync interface mode. Cascading devices allows multiple devices to share the same interface bus and reduces pin connections to the host processor.

9.1.2.1.1 SPI interface Mode

In SPI interface mode, CLK, SCLK, DIN, and DOUT from each device are shared with independent CS signals. Monitor the DRDY signal from only one device. Leave the remaining DRDY pins floating. Figure 103 shows the required connections for cascading multiple devices in SPI interface mode.

Figure 103. Cascaded Devices in SPI Interface Mode

The host processor must use a separate GPIO to control the CS pins on each ADS127L01 device. When CS is driven to a logic 1, the DOUT of that device is high-impedance. This structure allows another device to take control of the DOUT bus. The SCLK frequency must be high enough to read all of the data from each device before the next DRDY pulse arrives. Alternatively, tie the DOUT pin from each device to a separate pin on the host processor to collect data from multiple devices in parallel.

Equation 9 calculates the maximum number of devices that can share the same bus in a cascaded configuration in terms of data rate, SCLK frequency, and total number of bits per device.

Equation 9. Number of Devices ≤ (t_DATA – t_CSDO – t_CSDOZ) / (n × t_SCLK)

where

• n = 24 or 32 bits

9.1.2.1.2 Frame-Sync interface Mode

In frame-sync interface mode, the CS pin is unused and must be tied to DGND. CLK, SCLK, DIN, and FSYNC from each device are shared with independent DOUT signals. Connect the DOUT pin from each device to a separate input pin on the host processor to read the data from multiple devices in parallel. Figure 104 shows the required connections for cascading multiple devices in frame-sync interface mode.

Figure 104. Cascaded Devices in Frame-Sync Mode

Only one device can be configured in frame-sync master mode; remaining devices must be configured in frame-sync slave mode. Otherwise, configure all devices in frame-sync slave mode.

Equation 10 calculates the maximum number of devices that can be daisy-chained for SPI and frame-sync slave mode in terms of data rate, SCLK frequency, and total number of bits to read from each device.

Equation 10. Number of Devices ≤ (t_DATA) / (n × t_SCLK)

where

• n = 24 or 32 bits

9.1.2.2 Daisy-Chain Configuration

Two or more ADS127L01 devices can be daisy-chained together in either SPI interface mode or frame-sync slave mode. Frame-sync master mode does not support daisy-chain configurations. For both SPI and frame-sync slave mode, connect the DOUT pin of the first device in the chain to an input pin on the host processor. Connect the DOUT pin of the remaining devices to the DAISYIN pin of the next device. Connect the DAISYIN pin on the last device to DGND.

Equation 11 calculates the maximum number of devices that can share the same bus in a cascaded configuration in terms of data rate, SCLK frequency, and total number of bits per device.

9.1.2.2.1 Daisy-Chain Operation Using SPI interface Mode

In SPI interface mode, CLK, SCLK, DIN and CS are shared. Monitor only the DRDY signal from one device. Leave the remaining DRDY pins floating. The SCLK frequency must be high enough to read all the data from each device before the next DRDY pulse arrives. Figure 105 shows the required connections for daisy-chaining multiple devices in SPI interface mode.

Figure 105. Daisy-Chained Devices in SPI Mode

All data from Device 0 is shifted into Device 1 on the DAISYIN pin. The MSB from the Device 0 data immediately follows the LSB from Device 1 on the DOUT pin of Device 0. Figure 106 illustrates the timing relationship for daisy-chaining devices in SPI interface mode.

Figure 106. Daisy-Chain Timing in SPI interface Mode

9.1.2.2.2 Daisy-Chain Operation Using Frame-Sync interface Mode

In frame-sync slave mode, CLK, SCLK, DIN and FSYNC are shared. The CS pin is unused and must be tied to DGND. The SCLK frequency must be high enough to read all the data from each device before the next frame begins. Figure 107 shows the required connections for daisy-chaining multiple devices in frame-sync slave mode.

Figure 107. Daisy-Chained Devices in Frame-Sync Slave Mode

All data from Device 1 are shifted into Device 0 on the DAISYIN pin. The MSB from the Device 1 data immediately follows the LSB from Device 0 on the DOUT pin of Device 1. Figure 108 illustrates the timing relationship for daisy-chaining devices in frame-sync slave mode.

Figure 108. Daisy-Chain Timing in Frame-Sync Slave Mode

9.1.2.3 Synchronizing Devices

Use the START pin or the RESET/PWDN pin to synchronize multiple devices. The START pin does not reset the device registers to the default settings. The RESET/PWDN pin resets the device to the factory default settings, and resets the interface when in frame-sync master mode. The delay from the START signal high to the first data ready is fixed for a given data rate (see the Start Pin (START) section for more details on the delay times).

An alternate way to synchronize multiple devices is using the RESET/PWDN pin. The RESET/PWDN pin resets the digital interface in addition to the digital filters and registers, making it the recommended synchronization method for frame-sync master mode. The delay from the RESET/PWDN pin high to the first data ready is fixed for a given data rate (see the Reset and Power-Down Pin (RESET/PWDN) section for more details on the delay times). The RESET/PWDN pin is also used to synchronize multiple devices in SPI interface mode or frame-sync slave mode.

When synchronizing multiple devices, the master clock, f_clk, must be shared from the same signal source.

9.1.3.1 Antialiasing Filter

Signal aliasing in data-acquisition systems occurs when continuous-time signals are discretely sampled at a constant rate. To properly represent an analog signal in the digital domain, the system must sample the input at a sampling rate greater than twice the maximum frequency content, known as the Nyquist rate. Frequencies that are greater than one-half the sampling rate are not represented properly in the digital domain and appear as aliases of the original input instead.

Delta-sigma ADCs exhibit two Nyquist frequencies, as shown in Figure 109. The first Nyquist frequency occurs in the analog domain at one-half the modulator sampling rate (f_MOD / 2). The second Nyquist frequency occurs in the digital domain at one-half the decimated output data rate (f_DATA / 2). Frequency content repeats at multiples of f_MOD and f_DATA. Both Nyquist frequencies allow for out-of-band signals to alias into the ADC pass band, including noise from the front-end driver circuit. This aliasing increases the in-band noise level of the system and degrades overall performance if not adequately filtered.

Figure 109. Delta-Sigma ADC Internal Signal Chain

Figure 110 and Figure 111 illustrate the two aliasing domains in delta-sigma ADCs. Figure 110 shows a higher-frequency, out-of-band signal aliasing around the modulator Nyquist frequency (f_MOD / 2) into the pass band. Figure 111 shows a lower-frequency, out-of-band signal aliasing around the data rate Nyquist frequency (f_DATA / 2) into the pass band after being attenuated by the digital filter.

Figure 110. Analog Domain Aliasing Around f_MOD / 2

Figure 111. Digital Domain Aliasing Around f_DATA / 2

To prevent signals from aliasing, use a low-pass antialiasing filter to attenuate the out-of-band signals. The simplest antialiasing filter is a discrete first-order, low-pass, RC filter. To achieve a higher level of attenuation at the Nyquist frequency requires a higher-order filter response, usually before the last amplifier stage.

The digital filter in delta-sigma ADCs reduces the attenuation requirement of the antialiasing filter by providing a high stop-band attenuation between f_DATA / 2 and f_MOD. At multiples of f_MOD, the digital filter response returns to 0 dB and repeats. This portion of the digital filter response is the sensitive frequency band where an antialiasing filter is needed. Figure 112 overlays a digital filter response with first-, second-, and third-order antialiasing filters, attenuating both out-of-band signals.

Figure 112. Antialiasing and Digital Filters

The antialiasing RC filter also helps to attenuate the voltage transients from the sampling network at the ADC inputs. Figure 113 shows a simplified switch-capacitor circuit at the inputs of an ADC modulator. The sampling network, described in Figure 60, places a transient load on the external drive circuit. The differential capacitor in the RC filter, C_DIFF, acts as a charge reservoir and transfers charge to the internal sampling capacitor, C_SAMPLE, while S1 is closed. The input driver circuit must restore the charge at the input nodes (AINP and AINN) so that the voltage settles before S1 opens. After S1 opens, S2 closes, discharging the C_SAMPLE capacitor. The faster the modulator sampling rate, the less time the input voltage has to settle. An amplifier with a gain-bandwidth product (GBP) that is too low fails to provide adequate settling because of the higher output impedance over frequency, and results in increased distortion.

Figure 113. Delta-Sigma Modulator Sampling Network

The sampling capacitors of the ADS127L01 have an equivalent capacitance of 8 pF. Scale C_DIFF to be at least 100 times larger than C_SAMPLE. Connect C_DIFF directly across the ADC input pins to help provide adequate charge with each ADC sample. C_DIFF must be C0G or NP0 dielectric type because these components have a high-Q, low-temperature coefficient, and stable electrical characteristics to withstand varying voltages and frequencies. Common-mode capacitors, C_CM, can also be added at each input to ground to attenuate common-mode noise and sampling glitches. Size the common-mode capacitors to be one order of magnitude smaller than C_DIFF in order to maintain system common-mode rejection (CMR).

Figure 114 shows an example of the voltage transient created by the ADC sampling event at the inputs of an unbuffered delta-sigma ADC. The larger transients mark the moment when S1 closes to connect C_SAMPLE to the external front-end circuitry. The smaller transient occurs when the S1 switch opens passing the charge through the modulator. The sequence repeats at 1 / f_MOD. The data were recorded using a passive 10x probe on the AINP pin only. The same transient is observed on AINN as well. The differential transient voltage is more than an order of magnitude smaller.

Figure 114. ADC Input During Sampling

When S1 opens, the input signal is sampled and converted by the modulator. Increasing C_DIFF provides a larger charge reservoir to the ADC, and reduces the initial voltage droop. For ADCs with a faster sampling frequency, there is less time for this voltage transient to fully settle before the next sample. The ADC input relies on a driver amplifier with sufficient bandwidth and low output impedance at high frequencies to provide recovery charge and fully settle the voltage transient before S1 opens.

9.1.3.2 Input Driver Selection

Selection criteria for the input amplifiers are highly dependent on the input signal type, as well as the performance goals of the data-acquisition system. Consider the following amplifier specifications when selecting the appropriate driver amplifier for the application:

• Noise. The output noise density of the front-end amplifiers must be kept as low as possible to prevent any degradation in system SNR performance. The total noise from the input stage is determined by the –3-dB bandwidth of the ADS127L01 digital filter. Make sure that the total output noise is less than 20% of the input-referred noise of the ADC, as explained in Equation 12:
Equation 12.
where
• e_{o_RMS} = Broadband output noise of the input driver stage in nV/√Hz
• f_-3dB = –3-dB bandwidth of the ADS127L01 digital filter in Hz
• Distortion. Keep the distortion from the front-end drivers as low as possible, especially in the presence of a switching load. Harmonics produced by the amplifier are also compounded by harmonics produced by the ADC. Minimize the amplifier distortion by using the widest allowable supply voltage and highest output load resistance for the application. Select an amplifier with high open-loop gain and at least –10 dB better distortion than the ADC distortion in order to prevent any degradation to system THD performance, as explained by Equation 13.
Equation 13.
where
• THD_AMP = Total harmonic distortion from input driver
• THD_ADC = Total harmonic distortion specification of the ADC
• Small-signal bandwidth. Select the small-signal bandwidth of the input amplifiers to be as high as possible, after meeting the power budget of the system. Higher bandwidth reduces the closed-loop output impedance of the amplifier, thus allowing the amplifier to more easily drive a larger capacitive load with a smaller series resistor. For a given low-pass filter cutoff, keep the series resistor as small as possible and increase the differential capacitor to minimize gain error and distortion (see the Antialiasing Filter section). Higher bandwidth also minimizes harmonic distortion caused by faster settling of the input transients from the ADC sampling. The required amplifier bandwidth depends on the size of the sampling capacitor, the sampling frequency, and the size of the external differential capacitor. TINA-TI simulations help model the small-signal settling behavior and the stability of the input driver circuit for a given load.

The THS45xx family of fully-differential amplifiers offers the low noise and distortion specifications needed in high-performance data-acquisition systems. Table 30 shows the power versus performance tradeoff offered between the THS4531A, THS4551, and the highest performing THS4541.

Figure 115 and Figure 116 compare the distortion and noise performance of the THS4531A, THS4541, and THS4551 as they drive the inputs of the ADS127L01. Each input driver circuit was configured for a gain of one using the nominal feedback resistor values in Table 30. An AP2700 function generator provided a full-scale, sine wave input at frequencies of 2 kHz and below, such that at least five harmonics were present in the fast Fourier transform (FFT) calculated from 8,192 samples. An Agilent 33522A provided the clock input for the ADS127L01 (CLK) to set the modulator clock frequency between 100 kHz and 16.384 MHz.

To quantify the distortion performance of each input driver circuit, the spurious-free dynamic range (SFDR) is calculated at each modulator clock frequency. A third-order polynomial, best-fit curve is applied to the raw data to show the overall trend for each amplifier.

Figure 115 illustrates that at slower modulator clock frequencies, a lower power amplifier with less bandwidth can be used to achieve similar SFDR performance as higher power amplifiers with more bandwidth. However, faster modulator clock frequencies require the use of a wide-bandwidth amplifier to get the best performance out of the ADC.

Figure 115. SFDR vs f_MOD

In contrast to SFDR, the signal-to-noise ratio (SNR) of a data-acquisition signal chain is more dependent on the input amplifier noise density, as well as the ADC output data rate. Figure 116 displays the SNR performance of the ADS127L01 measured while driving the inputs with the THS4531A, THS4541, and THS4551. The digital filter in the ADS127L01 is configured to use the Wideband 2 transition band and an OSR of 256 throughout the SNR measurements. An AP2700 provided a small-signal 1 kHz input sine wave of 100 mVpp. An Agilent 33522A provided the clock input (CLK) for the ADS127L01 to set the modulator clock frequency between 100 kHz and 16.384 MHz. The measured SNR is normalized to full-scale.

Figure 116. SNR vs f_MOD

The SNR performance is expected to remain relatively constant for all three amplifiers across modulator frequencies. However, the improvement in SNR at slower modulator frequencies is because of the reduced bandwidth of the digital filter as it scales down with modulator clock, limiting the input source broadband noise. At higher frequencies, noise from the input source dominates as the digital-filter bandwidth increases. The difference in amplifier noise density, listed in Table 30, has the largest effect on the system noise performance.

9.1.3.3 Amplifier Stability

Driving a capacitive load can degrade the phase margin of the input amplifier, and can make the amplifier unstable. To prevent the amplifier from becoming unstable, a series isolation resistor (R_FLT) is used at the amplifier output, as shown in Figure 113. A higher resistance value increases phase margin and makes the amplifier more stable, but also increases distortion caused by the interaction with the nonlinear input impedance of the ADC modulator. Distortion increases with source output impedance, input-signal frequency, and input-signal amplitude.

The selection of R_FLT requires a balance between distortion and the stability of the input driver design. The use of 1% components is allowed because the C_DIFF mitigates the degradation of CMR caused by input imbalances.

The input amplifier must be selected with a bandwidth higher than the cutoff frequency, f_C, of the antialiasing filter at the ADC inputs. Use a TINA-TI simulation to confirm that the amplifier has more than 30° of phase margin when driving the selected filter to verify stability. Simulation is critical because some amplifiers require more bandwidth than others to drive the same filter. If the input amplifier circuit has less than 20° of phase margin, consider adding a capacitor at the amplifier inputs to increase phase margin.

Table 31. Differential Input Amplitude Limits (dBFS)

9.1.5.1 Single Chip Solution: REF6xxx

The REF6xxx is a family of very high-precision, low-noise, and low-drift voltage references. This single-chip solution has an integrated high-bandwidth buffer that presents a low output impedance to the ADC reference input. The REF6025 outputs a fixed 2.5-V output voltage; however, other devices from the same family are available to offer various output voltages and temperature drift specifications

The ADS127L01 has the ability to maintain a high level of performance at relatively low levels of power consumption. The REF6025 only adds 750 μA of typical quiescent current to the system power budget, while still showcasing the performance of the ADS127L01 when sampling at full-speed, making it a great fit for low-power applications with limited board space.

Figure 117 shows typical connections for the REF6025 as a reference driver circuit to the ADS127L01. The output of the REF6025 uses a Kelvin connection to correct for the voltage drop between the voltage output pins and the pads of the output capacitor. A small series resistance is required to keep the reference output stable. See the REF60xx device datasheet (SBOS708) for more details on the required connections and component values.

Figure 117. REF6025 Connection to ADS127L01

9.1.5.2 Multichip Solution: REF50xx + OPA320

The REF50xx is another family of low-noise, low-drift, high-precision voltage references. The REF5025 outputs a fixed 2.5-V output voltage; however, other devices from the same family are available to offer various output voltages. Buffer the output of the REF5025 with a low-noise, wide bandwidth amplifier such as the OPA320 to achieve the best performance with the ADS127L01.

The OPA320 is a precision, low-voltage CMOS operational amplifier optimized for low noise and wide bandwidth with a typical quiescent current of 1.5 mA. From 0.1 Hz to 10 Hz, the OPA320 features an output noise of 2.8 µV_PP. With a unity gain-bandwidth product of 20 MHz, the OPA320 is able to drive the ADS127L01 reference inputs while sampling at full-speed without degrading linear performance of the system.

Figure 118 shows an example reference circuit using the REF5025 and the OPA320. The output of the REF5025 is low-pass filtered to less than 2 Hz before the input of the OPA320. The OPA320 is placed in a noninverting buffer configuration with dual-feedback to compensate for the large capacitive output load and maintain stability. See the respective device data sheets for more details on the required connections and component values.

Figure 118. REF5025 + OPA320 Connection to ADS127L01

Table 32. Reference Selection

Table 33. Design Requirements

Table 34. Power Consumption