SBAS607B April   2016  – September 2016 ADS127L01

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: Serial Interface
    7. 6.7  Switching Characteristics: Serial Interface Mode
    8. 6.8  Timing Requirements: Frame-Sync Master Mode
    9. 6.9  Switching Characteristics: Frame-Sync Master Mode
    10. 6.10 Timing Requirements: Frame-Sync Slave Mode
    11. 6.11 Switching Characteristics: Frame-Sync Slave Mode
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement information
    1. 7.1 Noise Performance
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Inputs (AINP, AINN)
      2. 8.3.2 Digital Filter
        1. 8.3.2.1 Low-Latency Filter
          1. 8.3.2.1.1 Low-Latency Filter Frequency Response
          2. 8.3.2.1.2 Low-Latency Filter Settling Time
        2. 8.3.2.2 Wideband Filter
          1. 8.3.2.2.1 Wideband Filters Frequency Response
          2. 8.3.2.2.2 Wideband Filters Settling Time
      3. 8.3.3 Voltage Reference Inputs (REFP, REFN)
      4. 8.3.4 Clock Input (CLK)
      5. 8.3.5 Out-of-Range-Detect System Monitor
      6. 8.3.6 System Calibration
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operating Modes (HR, LP, VLP)
      2. 8.4.2 Hardware Mode Pins
        1. 8.4.2.1 Interface Selection Pins (FORMAT, FSMODE)
        2. 8.4.2.2 Digital-Filter Path Selection Pins (FILTER[1:0])
        3. 8.4.2.3 Oversampling Ratio Selection Pins (OSR[1:0])
      3. 8.4.3 Start Pin (START)
      4. 8.4.4 Reset and Power-Down Pin (RESET/PWDN)
    5. 8.5 Programming
      1. 8.5.1 Serial Peripheral Interface (SPI) Programming
        1. 8.5.1.1 Chip Select (CS)
        2. 8.5.1.2 Serial Clock (SCLK)
        3. 8.5.1.3 Data Ready (DRDY/FSYNC)
        4. 8.5.1.4 Data Input (DIN)
        5. 8.5.1.5 Data Output (DOUT)
        6. 8.5.1.6 Daisy-Chain Input (DAISYIN)
        7. 8.5.1.7 SPI Timeout
        8. 8.5.1.8 SPI Commands
          1. 8.5.1.8.1 RESET (0000 011x)
          2. 8.5.1.8.2 START (0000 100x)
          3. 8.5.1.8.3 STOP (0000 101x)
          4. 8.5.1.8.4 RDATA (0001 0010)
          5. 8.5.1.8.5 RREG (0010 rrrr 0000 nnnn)
          6. 8.5.1.8.6 WREG (0100 rrrr 0000 nnnn)
      2. 8.5.2 Frame-Sync Programming
        1. 8.5.2.1 Frame-Sync Master Mode
          1. 8.5.2.1.1 Chip Select (CS) in Frame-Sync Master Mode
          2. 8.5.2.1.2 Serial Clock (SCLK) in Frame-Sync Master Mode
          3. 8.5.2.1.3 Frame-Sync (DRDY/FSYNC) in Frame-Sync Master Mode
          4. 8.5.2.1.4 Data Input (DIN) in Frame-Sync Master Mode
          5. 8.5.2.1.5 Data Output (DOUT) in Frame-Sync Master Mode
          6. 8.5.2.1.6 Daisy-Chain Input (DAISYIN) in Frame-Sync Master Mode
        2. 8.5.2.2 Frame-Sync Slave Mode
          1. 8.5.2.2.1 Chip Select (CS) in Frame-Sync Slave Mode
          2. 8.5.2.2.2 Serial Clock (SCLK) in Frame-Sync Slave Mode
          3. 8.5.2.2.3 Frame-Sync (DRDY/FSYNC) in Frame-Sync Slave Mode
          4. 8.5.2.2.4 Data Input (DIN) in Frame-Sync Slave Mode
          5. 8.5.2.2.5 Data Output (DOUT) in Frame-Sync Slave Mode
          6. 8.5.2.2.6 Daisy-Chain Input (DAISYIN) in Frame-Sync Slave Mode
      3. 8.5.3 Data Format
      4. 8.5.4 Status Word
      5. 8.5.5 Cyclic Redundancy Check (CRC)
        1. 8.5.5.1 Computing the CRC
    6. 8.6 Register Maps
      1. 8.6.1 ID: ID Control Register (address = 00h) [reset = x3h]
      2. 8.6.2 CONFIG: ADC Configuration Register (address = 01h) [reset = 00h]
      3. 8.6.3 OFC0: System Offset Calibration Register 0 (address = 02h) [reset = 00h]
      4. 8.6.4 OFC1: System Offset Calibration Register 1 (address = 03h) [reset = 00h]
      5. 8.6.5 OFC2: System Offset Calibration Register 2 (address = 04h) [reset = 00h]
      6. 8.6.6 FSC0: System Gain Calibration Register 0 (address = 05h) [reset = 00h]
      7. 8.6.7 FSC1: System Gain Calibration Register 1 (address = 06h) [reset = 80h]
      8. 8.6.8 MODE: Mode Settings (address = 07h) [reset = xxh]
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Unused Inputs and Outputs
      2. 9.1.2 Multiple Device Configuration
        1. 9.1.2.1 Cascaded Configuration
          1. 9.1.2.1.1 SPI interface Mode
          2. 9.1.2.1.2 Frame-Sync interface Mode
        2. 9.1.2.2 Daisy-Chain Configuration
          1. 9.1.2.2.1 Daisy-Chain Operation Using SPI interface Mode
          2. 9.1.2.2.2 Daisy-Chain Operation Using Frame-Sync interface Mode
        3. 9.1.2.3 Synchronizing Devices
      3. 9.1.3 ADC Input Driver
        1. 9.1.3.1 Antialiasing Filter
        2. 9.1.3.2 Input Driver Selection
        3. 9.1.3.3 Amplifier Stability
      4. 9.1.4 Modulator Saturation
      5. 9.1.5 ADC Reference Driver
        1. 9.1.5.1 Single Chip Solution: REF6xxx
        2. 9.1.5.2 Multichip Solution: REF50xx + OPA320
      6. 9.1.6 Driving LVDD With an External Supply
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
    4. 9.4 Initialization Setup
  10. 10Power Supply Recommendations
    1. 10.1 Power-Supply Sequencing
    2. 10.2 Power-Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

PBS package
32-Pin TQFP
Top View

Pin Functions

PIN I/O DESCRIPTION(3)
NO. NAME
1 LVDD Supply LVDD analog supply.
INTLDO = 0: LVDD is an analog-supply output pin. Connect a 1-µF capacitor to AGND.
INTLDO = 1: LVDD is an analog-supply input pin. Connect to a 1.8-V supply.
2 CAP1 Analog output Modulator common-mode voltage.
Connect a 1-µF capacitor to AGND
3 AINN Analog input Negative analog input.
4 AINP Analog input Positive analog input.
5 AGND Supply Analog ground.
6 AVDD Supply Analog supply.
Connect a 1-μF capacitor to AGND.
7 REXT Analog input Analog power-scaling bias resistor pin.
Recommended external resistor values:
REXT = 60.4 kΩ to AGND for high-resolution (HR) and low-power (LP) modes
REXT = 120 kΩ to AGND for very-low-power (VLP) mode
8 INTLDO Digital input LVDD voltage selection pin (pull high to AVDD or low to AGND through 10-kΩ resistor).
0: Internal analog low-dropout regulator (LDO) for LVDD voltage supply.
1: External LVDD voltage supply.
9 REFP Analog input Positive analog reference input.
Connect a minimum 10-μF capacitor to REFN
10 REFN Analog input Negative analog reference input.
11 CAP2 Analog output Reference common-mode voltage.
Connect a 1-µF capacitor to AGND.
12 FILTER1 Digital input Digital filter select pin(1).
00: Wideband 1 filter (WB1)
01: Wideband 2 filter (WB2)
10: Low-latency filter (LL)
11: Reserved
13 FILTER0 Digital input
14 FSMODE Digital input Frame-sync mode pin(1).
0: Slave mode
1: Master mode. Applies to Frame-Sync interface mode only. No effect in SPI interface mode.
15 OSR1 Digital input Oversampling ratio (OSR) pin for the decimation filters(1).

Wideband filters, FILTER[1:0] = 00 or 01:
00: 32x oversampling (OSR 32)
01: 64x oversampling (OSR 64)
10: 128x oversampling (OSR 128)
11: 256x oversampling (OSR 256)

Low-latency filter, FILTER[1:0] = 10:
00: 32x oversampling (OSR 32)
01: 128x oversampling (OSR 128)
10: 512x oversampling (OSR 512)
11: 2048x oversampling (OSR 2048)
16 OSR0 Digital input
17 START Digital input Synchronization signal to start or restart a conversion.
18 DAISYIN Digital input Daisy-chain input.
19 DRDY/FSYNC Digital input/output SPI interface: Data ready, active low(2).
Frame-sync interface: Frame-sync input signal(2)
20 DOUT Digital output Serial data output
21 DIN Digital input Serial data input.
Tie directly to DGND when using the frame-sync interface.
22 SCLK Digital input/output Serial clock input(2).
23 CS Digital input Chip select.
Tie directly to DGND when using the frame-sync interface.
24 CLK Digital input Master clock input.
25 CAP3 Analog output Internally-generated digital operating voltage.
Connect a 1-µF capacitor to DGND.
26 DGND Supply Digital ground.
27 DVDD Supply Digital supply.
Connect a 1-μF capacitor to DGND(2)
28 RESET/PWDN Digital input Reset or power-down pin, active low(2).
29 HR Digital input ADC operating mode(1).
1: High-resolution (HR)
0: Low-power (LP) or very-low-power (VLP)(4)
30 FORMAT Digital input Interface select pin(1).
0: SPI
1: Frame-Sync
31 AGND Supply Analog ground.
32 AVDD Supply Analog supply.
Decouple AVDD to AGND with a 1-μF capacitor.
(1) Pull the hardware mode pins high to DVDD or low to DGND through 100-kΩ resistors.
(2) See the Reset and Power-Down Pin (RESET/PWDN) section for specific hardware design details if using power-down mode.
(3) See the Unused Inputs and Outputs section for unused pin connections.
(4) Entering LP mode or VLP mode is set by REXT resistor value.