SBAS607B April   2016  – September 2016 ADS127L01

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: Serial Interface
    7. 6.7  Switching Characteristics: Serial Interface Mode
    8. 6.8  Timing Requirements: Frame-Sync Master Mode
    9. 6.9  Switching Characteristics: Frame-Sync Master Mode
    10. 6.10 Timing Requirements: Frame-Sync Slave Mode
    11. 6.11 Switching Characteristics: Frame-Sync Slave Mode
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement information
    1. 7.1 Noise Performance
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Inputs (AINP, AINN)
      2. 8.3.2 Digital Filter
        1. 8.3.2.1 Low-Latency Filter
          1. 8.3.2.1.1 Low-Latency Filter Frequency Response
          2. 8.3.2.1.2 Low-Latency Filter Settling Time
        2. 8.3.2.2 Wideband Filter
          1. 8.3.2.2.1 Wideband Filters Frequency Response
          2. 8.3.2.2.2 Wideband Filters Settling Time
      3. 8.3.3 Voltage Reference Inputs (REFP, REFN)
      4. 8.3.4 Clock Input (CLK)
      5. 8.3.5 Out-of-Range-Detect System Monitor
      6. 8.3.6 System Calibration
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operating Modes (HR, LP, VLP)
      2. 8.4.2 Hardware Mode Pins
        1. 8.4.2.1 Interface Selection Pins (FORMAT, FSMODE)
        2. 8.4.2.2 Digital-Filter Path Selection Pins (FILTER[1:0])
        3. 8.4.2.3 Oversampling Ratio Selection Pins (OSR[1:0])
      3. 8.4.3 Start Pin (START)
      4. 8.4.4 Reset and Power-Down Pin (RESET/PWDN)
    5. 8.5 Programming
      1. 8.5.1 Serial Peripheral Interface (SPI) Programming
        1. 8.5.1.1 Chip Select (CS)
        2. 8.5.1.2 Serial Clock (SCLK)
        3. 8.5.1.3 Data Ready (DRDY/FSYNC)
        4. 8.5.1.4 Data Input (DIN)
        5. 8.5.1.5 Data Output (DOUT)
        6. 8.5.1.6 Daisy-Chain Input (DAISYIN)
        7. 8.5.1.7 SPI Timeout
        8. 8.5.1.8 SPI Commands
          1. 8.5.1.8.1 RESET (0000 011x)
          2. 8.5.1.8.2 START (0000 100x)
          3. 8.5.1.8.3 STOP (0000 101x)
          4. 8.5.1.8.4 RDATA (0001 0010)
          5. 8.5.1.8.5 RREG (0010 rrrr 0000 nnnn)
          6. 8.5.1.8.6 WREG (0100 rrrr 0000 nnnn)
      2. 8.5.2 Frame-Sync Programming
        1. 8.5.2.1 Frame-Sync Master Mode
          1. 8.5.2.1.1 Chip Select (CS) in Frame-Sync Master Mode
          2. 8.5.2.1.2 Serial Clock (SCLK) in Frame-Sync Master Mode
          3. 8.5.2.1.3 Frame-Sync (DRDY/FSYNC) in Frame-Sync Master Mode
          4. 8.5.2.1.4 Data Input (DIN) in Frame-Sync Master Mode
          5. 8.5.2.1.5 Data Output (DOUT) in Frame-Sync Master Mode
          6. 8.5.2.1.6 Daisy-Chain Input (DAISYIN) in Frame-Sync Master Mode
        2. 8.5.2.2 Frame-Sync Slave Mode
          1. 8.5.2.2.1 Chip Select (CS) in Frame-Sync Slave Mode
          2. 8.5.2.2.2 Serial Clock (SCLK) in Frame-Sync Slave Mode
          3. 8.5.2.2.3 Frame-Sync (DRDY/FSYNC) in Frame-Sync Slave Mode
          4. 8.5.2.2.4 Data Input (DIN) in Frame-Sync Slave Mode
          5. 8.5.2.2.5 Data Output (DOUT) in Frame-Sync Slave Mode
          6. 8.5.2.2.6 Daisy-Chain Input (DAISYIN) in Frame-Sync Slave Mode
      3. 8.5.3 Data Format
      4. 8.5.4 Status Word
      5. 8.5.5 Cyclic Redundancy Check (CRC)
        1. 8.5.5.1 Computing the CRC
    6. 8.6 Register Maps
      1. 8.6.1 ID: ID Control Register (address = 00h) [reset = x3h]
      2. 8.6.2 CONFIG: ADC Configuration Register (address = 01h) [reset = 00h]
      3. 8.6.3 OFC0: System Offset Calibration Register 0 (address = 02h) [reset = 00h]
      4. 8.6.4 OFC1: System Offset Calibration Register 1 (address = 03h) [reset = 00h]
      5. 8.6.5 OFC2: System Offset Calibration Register 2 (address = 04h) [reset = 00h]
      6. 8.6.6 FSC0: System Gain Calibration Register 0 (address = 05h) [reset = 00h]
      7. 8.6.7 FSC1: System Gain Calibration Register 1 (address = 06h) [reset = 80h]
      8. 8.6.8 MODE: Mode Settings (address = 07h) [reset = xxh]
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Unused Inputs and Outputs
      2. 9.1.2 Multiple Device Configuration
        1. 9.1.2.1 Cascaded Configuration
          1. 9.1.2.1.1 SPI interface Mode
          2. 9.1.2.1.2 Frame-Sync interface Mode
        2. 9.1.2.2 Daisy-Chain Configuration
          1. 9.1.2.2.1 Daisy-Chain Operation Using SPI interface Mode
          2. 9.1.2.2.2 Daisy-Chain Operation Using Frame-Sync interface Mode
        3. 9.1.2.3 Synchronizing Devices
      3. 9.1.3 ADC Input Driver
        1. 9.1.3.1 Antialiasing Filter
        2. 9.1.3.2 Input Driver Selection
        3. 9.1.3.3 Amplifier Stability
      4. 9.1.4 Modulator Saturation
      5. 9.1.5 ADC Reference Driver
        1. 9.1.5.1 Single Chip Solution: REF6xxx
        2. 9.1.5.2 Multichip Solution: REF50xx + OPA320
      6. 9.1.6 Driving LVDD With an External Supply
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
    4. 9.4 Initialization Setup
  10. 10Power Supply Recommendations
    1. 10.1 Power-Supply Sequencing
    2. 10.2 Power-Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings(1)

MIN MAX UNIT
Voltage AVDD to AGND –0.3 4.0 V
DVDD to DGND –0.3 4.0
LVDD to AGND –0.3 2.0
AGND to DGND –0.3 0.3
REFP to AGND –0.3 AVDD + 0.3
REFN to AGND –0.3 AVDD + 0.3
Analog input AGND – 0.3 AVDD + 0.3
Digital input DGND – 0.3 DVDD + 0.3
Current Input, continuous, any pin except power supply pins (2) –10 10 mA
Temperature Operating ambient, TA –40 125 °C
Junction, TJ 150
Storage, Tstg –60 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins are diode-clamped to the power-supply rails. Limit the input current to 10 mA or less if the analog input voltage exceeds AVDD + 0.3 V or is less than AGND – 0.3 V, or if the digital input voltage exceeds DVDD + 0.3 V or is less than DGND – 0.3 V.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)
MIN NOM MAX UNIT
POWER SUPPLY
AVDD Analog power supply 2.7 3.0 3.6 V
LVDD Low voltage analog supply INTLDO = 1 1.7 1.8 1.9 V
DVDD Digital supply 1.7 1.8 3.6 V
ANALOG INPUTS
VIN Differential input voltage VIN = (VAINP – VAINN) –VREF VREF V
VAINP, VAINN Absolute input voltage AINP or AINN to AGND AGND AVDD V
VCM Common-mode input voltage VCM = (VAINP + VAINN) / 2 AVDD / 2 V
VOLTAGE REFERENCE INPUTS
VREFN Negative reference input AGND – 0.1 AGND AGND + 1.0 V
VREFP Positive reference input VREFN + 0.5 2.5 AVDD V
VREF Reference input voltage VREF = VREFP – VREFN 0.5 2.5 3.0 V
EXTERNAL CLOCK SOURCE
fCLK Master clock rate(1) HR mode 0.1 16.384 17.6 MHz
LP mode 0.1 8.192 8.8
VLP mode 0.1 4.096 4.4
DIGITAL INPUTS
Input voltage DGND DVDD V
TEMPERATURE RANGE
TA Operating ambient temperature –40 125 °C
(1) To meet maximum speed conditions, fCLK duty cycle must be 49% < duty cycle < 51%.

6.4 Thermal Information

THERMAL METRIC(1) ADS127L01 UNIT
PBS (TQFP)
32 PINS
RθJA Junction-to-ambient thermal resistance 73.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 15.9 °C/W
RθJB Junction-to-board thermal resistance 26.7 °C/W
ψJT Junction-to-top characterization parameter 0.4 °C/W
ψJB Junction-to-board characterization parameter 26.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

Minimum and maximum specifications apply from TA = –40°C to +125°C. Typical specifications are at TA = 25°C.
All specifications are at AVDD = 3 V, LVDD = 1.8 V (external), DVDD = 1.8 V, VREF = 2.5 V, INTLDO = 1, FILTER[1:0] = 01 (WB2), and fCLK = 16.384 MHz for HR mode, 8.192 MHz for LP mode, or 4.096 MHz for VLP mode (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
Differential input impedance HR mode, fCLK = 16.384 MHz 5 kΩ
LP mode, fCLK = 8.192 MHz 11
VLP mode, fCLK = 4.096 MHz 23
DC PERFORMANCE
Resolution No missing codes 24 Bits
fDATA Data rate HR mode Wideband filters 512, 256, 128, 64 kSPS
Low-latency filter 512, 128, 32, 8
LP mode Wideband filters 256, 128, 64, 32
Low-latency filter 256, 64, 16, 4
VLP mode Wideband filters 128, 64, 32, 16
Low-latency filter 128, 32, 8, 2
INL Integral nonlinearity(1) HR mode VCM = AVDD / 2 2.5 10 ppm
LP mode VCM = AVDD / 2 1 5
VLP mode VCM = AVDD / 2 1 5
Offset error ±0.1 mV
Offset drift 1.5 3.0 μV/°C
Gain error 0.2 %FSR
Gain calibration accuracy 0.003%
Gain drift HR mode 0.8 3 ppm/°C
LP mode 0.4 2.5
VLP mode 0.2 2
Noise(2) HR mode WB2, OSR 32 10.6 μVRMS
WB2, OSR 64 7.3 10.1
WB2, OSR 128 5.1 7.2
WB2, OSR 256 3.6 5.2
CMRR Common-mode rejection ratio fCM = 60 Hz 95 dB
PSRR Power-supply rejection ratio fPS = 60 Hz AVDD 90 dB
DVDD 85
LVDD 80
AC PERFORMANCE
SNR Signal-to-noise ratio(2)(3) WB2, OSR 32 104.4 dB
WB2, OSR 64 104.9 107.8
WB2, OSR 128 107.9 110.9
WB2, OSR 256 110.6 113.9
WB2, OSR 32, VREF = 3 V 105.8
WB2, OSR 64, VREF = 3 V 109.3
WB2, OSR 128, VREF = 3 V 112
WB2, OSR 256, VREF = 3 V 115.5
THD Total harmonic distortion(4) HR mode, fIN = 4 kHz, VIN = –0.5 dBFS –113 dB
LP mode, fIN = 4 kHz, VIN = –0.5 dBFS –126
VLP mode, fIN = 4 kHz, VIN = –0.5 dBFS –129
SFDR Spurious-free dynamic range HR mode –115 dB
LP mode –130
VLP mode –130
DIGITAL FILTER RESPONSE: WIDEBAND
Bandwidth See Table 1
Pass-band ripple ±0.000032 dB
Transition band FILTER[1:0] = 00 (WB1) (0.45 to 0.55) × fDATA Hz
FILTER[1:0] = 01 (WB2) (0.40 to 0.50) × fDATA
Stop-band attenuation 116 dB
Group delay 42 / fDATA s
Settling time Complete settling 84 / fDATA s
DIGITAL FILTER RESPONSE: LOW-LATENCY
Bandwidth See Table 2
Group delay See Low-Latency Filter section
Settling time See Low-Latency Filter section
VOLTAGE REFERENCE INPUTS
Reference input impedance HR mode 2.2 kΩ
LP mode 3.2
VLP mode 4
SYSTEM MONITORS
Input over-range detect accuracy ±100 mV
DIGITAL INPUT/OUTPUT (DVDD = 1.7 V to 3.6 V)
VIH High-level input voltage 0.7 DVDD DVDD V
VIL Low-level input voltage DGND 0.3 DVDD V
VOH High-level output voltage IOH = 2 mA 0.8 DVDD DVDD V
VOL Low-level output voltage IOL = 2 mA DGND 0.2 DVDD V
IH Input leakage, high IH = 3.6 V –10 10 μA
IL Input leakage, low IL = DGND –10 10 μA
POWER SUPPLY
Power-down current AVDD INTLDO = 0 8 μA
INTLDO = 1 2
DVDD 0.6
LVDD, INTLDO = 1 0.6
IAVDD AVDD current HR mode 1.3 1.6 mA
LP mode 0.8 1.0
VLP mode 0.4 0.6
ILVDD LVDD current(5) (6) HR mode 9.3 11 mA
LP mode 4.6 5.5
VLP mode 2.3 2.8
IDVDD DVDD current(2) HR mode OSR 128 2.8 3.4 mA
LP mode OSR 128 1.5 1.8
VLP mode OSR 128 0.8 1.1
PD Power dissipation HR mode, OSR 128,
AVDD = 3.0 V,
DVDD = 1.8 V		 INTLDO = 1,
LVDD = 1.8 V, 		25.7 30.8 mW
INTLDO = 0 36.8 44.2
LP mode, OSR 128,
AVDD = 3.0 V,
DVDD = 1.8 V		 INTLDO = 1,
LVDD = 1.8 V, 		13.4 16.1
INTLDO = 0 18.9 22.7
VLP mode, OSR 128,
AVDD = 3.0 V,
DVDD = 1.8 V		 INTLDO = 1,
LVDD = 1.8 V, 		6.8 8.2
INTLDO = 0 9.5 11.4
(1) Best fit method.
(2) For all Wideband filter configurations, see Table 1. For all Low-latency filter configurations, see Table 2.
(3) Minimum SNR is ensured by the limit of the dc noise specification.
(4) THD includes the first nine harmonics of the input signal.
(5) LVDD current sourced from AVDD when the internal LDO is used (INTLDO = 0).
(6) LVDD current scales with fCLK; see Figure 47.

6.6 Timing Requirements: Serial Interface

over operating ambient temperature range (unless otherwise noted)
2.8 V < DVDD ≤ 3.6 V 1.7 V ≤ DVDD ≤ 2.8 V UNIT
MIN TYP MAX MIN TYP MAX
tc(CLK) Master clock period HR mode 57 10,000 57 10,000 ns
LP mode 114 10,000 114 10,000
VLP mode 227 10,000 227 10,000
tw(CP) Pulse duration, Master clock high or low HR mode 28 5,000 28 5,000 ns
LP mode 56 5,000 56 5,000
VLP mode 112 5,000 112 5,000
td(CSSC) Delay time, CS falling edge to first SCLK rising edge(1) 8 12 ns
tc(SC) SCLK period 40 6250 50 6250 ns
tw(SCHL) Pulse duration, SCLK high or low 20 25 ns
tsu(DI) Setup time, DIN valid before SCLK falling edge 6 9 ns
th(DI) Hold time, DIN valid after SCLK falling edge 8 9 ns
tw(CSH) Pulse duration, CS high 6 6 tCLK
td(SCCS) Delay time, final SCLK falling edge to CS rising edge 2 2 tCLK
td(DECODE) Delay time, command decode time 4 4 tCLK
SPI timeout(2) TOUT_DEL = 0 216 216 tCLK
TOUT_DEL = 1 214 214 tCLK
tsu(DCI) Setup time, DAISYIN valid before SCLK falling edge 5 8 ns
th(DCI) Hold time, DAISYIN valid after SCLK falling edge 20 25 ns
(1) CS can be tied low permanently in case the serial bus is not shared with any other device.
(2) See the SPI Timeout section for more information.

6.7 Switching Characteristics: Serial Interface Mode

over operating ambient temperature range (unless otherwise noted)
2.8 V < DVDD ≤ 3.6 V 1.7 V ≤ DVDD ≤ 2.8 V UNIT
MIN TYP MAX MIN TYP MAX
tp(CSDO) Propagation delay time,
CS falling edge to DOUT driven		 12 18 ns
tp(SCDO) Propagation delay time,
SCLK rising edge to valid new DOUT		 15 21 ns
tv(DO) Valid time, SCLK falling edge to DOUT invalid 18 tSCLK / 2 20 tSCLK / 2 ns
tp(CSDOZ) Propagation delay time,
CS rising edge to DOUT high impedance 		20 20 ns
ADS127L01 timing_SPI_sbas607.gif

NOINDENT:

NOTE: SPI settings are CPOL = 0 and CPHA = 1.
Figure 1. SPI Interface Timing
ADS127L01 timing_SPI_daisychain_sbas607.gif Figure 2. SPI Daisy-Chain Interface Timing

6.8 Timing Requirements: Frame-Sync Master Mode

over operating ambient temperature range and DVDD = 1.7 V to 3.6 V (unless otherwise noted)
1.7 V ≤ DVDD ≤ 3.6 V UNIT
MIN TYP MAX
tc(CLK) Master clock period HR mode 57 10,000 ns
LP mode 114 10,000
VLP mode 227 10,000
tw(CP) Pulse duration, Master clock high or low HR mode 28 5,000 ns
LP mode 56 5,000
VLP mode 112 5,000

6.9 Switching Characteristics: Frame-Sync Master Mode

over operating free-air temperature range (unless otherwise noted)
2.8 V < DVDD ≤ 3.6 V 1.7 V ≤ DVDD ≤ 2.8 V UNIT
MIN TYP MAX MIN TYP MAX
td(CSC) Delay time, CLK rising edge to SCLK falling edge 15 15 ns
tc(FRAME) Frame period 1 / fDATA 1 / fDATA s
tw(FP) Pulse duration, FSYNC high or low 1 / (2fDATA) 1 / (2fDATA) s
td(FSSC) Delay time, FSYNC rising edge to SCLK falling edge 6 8 ns
tc(SC) SCLK period 1 / (32fDATA) 1 / (32fDATA) s
tw(SCHL) Pulse duration, SCLK high or low 1 / (64fDATA) 1 / (64fDATA) s
tv(DO) Valid time, SCLK rising edge to DOUT invalid 25 25 ns
tp(SCDO) Propagation delay time,
SCLK falling edge to DOUT driven		 15 17 ns
tp(FSDO) Propagation delay time,
FSYNC rising edge to DOUT MSB valid		 12 15 ns
ADS127L01 timing_FSMaster_sbas607.gif Figure 3. Frame-Sync Interface Timing Master Mode

6.10 Timing Requirements: Frame-Sync Slave Mode

over operating ambient temperature range (unless otherwise noted)
2.8 V < DVDD ≤ 3.6 V 1.7 V ≤ DVDD ≤ 2.8 V UNIT
MIN TYP MAX MIN TYP MAX
tc(CLK) Master clock period HR mode 57 10,000 57 10,000 ns
LP mode 114 10,000 114 10,000
VLP mode 227 10,000 227 10,000
tw(CP) Pulse duration, Master clock high or low HR mode 28 5,000 28 5,000 ns
LP mode 56 5,000 56 5,000
VLP mode 112 5,000 112 5,000
td(CSC) Delay time, CLK rising edge to SCLK falling edge 2 2 ns
tc(FRAME) Frame period 1 / fDATA 1 / fDATA s
tw(FP) Pulse durration, FSYNC high or low 2 2 tSCLK
td(FSSC) Delay time, FSYNC rising edge to SCLK falling edge 6 6 ns
td(SCFS) Delay time, SCLK falling edge to FSYNC rising edge 2 2 ns
tc(SC) SCLK period 40 56 ns
tw(SCHL) Pulse duration, SCLK high or low 20 28 ns
DAISY-CHAIN TIMING
tsu(DCI) Setup time, DAISYIN valid before SCLK rising edge 8 8 ns
th(DCI) Hold time, DAISYIN valid after SCLK rising edge 25 31 ns

6.11 Switching Characteristics: Frame-Sync Slave Mode

over operating ambient temperature range (unless otherwise noted)
2.8 V < DVDD ≤ 3.6 V 1.7 V ≤ DVDD ≤ 2.8 V UNIT
MIN TYP MAX MIN TYP MAX
tv(DO) Valid time, SCLK rising edge to DOUT invalid 17 25 ns
tp(SCDO) Propagation delay time,
SCLK falling edge to valid new DOUT		 22 22 ns
tp(FSDO) Propagation delay time,
FSYNC rising edge to DOUT MSB valid		 15 22 25 32 ns
ADS127L01 timing_FSSlave_sbas607.gif Figure 4. Frame-Sync Interface Timing Slave Mode
ADS127L01 timing_FSSlave_daisychain_sbas607.gif Figure 5. Frame-Sync Interface Slave Daisy-Chain Timing

6.12 Typical Characteristics

At TA = 25°C, AVDD = 3.3 V, and external VREF = 2.5 V (unless otherwise noted)
ADS127L01 D026_sbas607.gif
fIN = 4 kHz, VIN = –0.5 dBFS, HR mode, WB2, 512 kSPS,
32768 samples
Figure 6. Output Spectrum
ADS127L01 D028_sbas607.gif
fIN = 4 kHz, VIN = –0.5 dBFS, HR mode, WB1, 512 kSPS,
32768 samples
Figure 8. Output Spectrum
ADS127L01 D030_sbas607.gif
fIN = 4 kHz, VIN = –0.5 dBFS, LP mode, WB2, 256 kSPS,
32768 samples
Figure 10. Output Spectrum
ADS127L01 D032_sbas607.gif
fIN = 4 kHz, VIN = –0.5 dBFS, VLP mode, WB2, 128 kSPS,
32768 samples
Figure 12. Output Spectrum
ADS127L01 D034_sbas607.gif
Inputs shorted, HR mode, WB2, 512 kSPS,
32768 samples
Figure 14. Output Spectrum
ADS127L01 D036_sbas607.gif
Inputs shorted, VLP mode, WB2, 128 kSPS,
32768 samples
Figure 16. Output Spectrum
ADS127L01 D040_sbas607.gif
Inputs shorted, HR mode, 65536 points
Figure 18. Noise Histogram
ADS127L01 D048_sbas607.gif
Inputs shorted
Figure 20. Noise vs Temperature
ADS127L01 D037_sbas607.gif
WB2, OSR 32
Figure 22. Total Harmonic Distortion vs fIN
ADS127L01 D052_sbas607.gif
HR mode, fIN = 4 kHz, VIN = –0.5 dBFS
Figure 24. Total Harmonic Distortion vs VREF
ADS127L01 D074_sbas607.gif
HR mode, fIN = 4 kHz, VIN = –0.5 dBFS
Figure 26. Total Harmonic Distortion Histogram
ADS127L01 D073_sbas607.gif
VLP mode, fIN = 4 kHz, VIN = –0.5 dBFS
Figure 28. Total Harmonic Distortion Histogram
ADS127L01 D051_sbas607.gif
Figure 30. INL vs VIN
ADS127L01 D041_sbas607.gif
Figure 32. Gain Error Histogram
ADS127L01 D049_sbas607.gif
Figure 34. Gain Error vs Temperature
ADS127L01 D044_sbas607.gif
HR mode, 30 Devices
Figure 36. Gain Drift Histogram
ADS127L01 D046_sbas607.gif
VLP mode, 30 Devices
Figure 38. Gain Drift Histogram
ADS127L01 D062_sbas607.gif
Inputs shorted, HR mode
Figure 40. Offset Voltage vs fCLK
ADS127L01 D076_SBAS607.gif
HR mode, INTLDO = 1
Figure 42. PSRR vs Power-Supply Frequency
ADS127L01 D056_sbas607.gif
Figure 44. IAVDD vs Temperature
ADS127L01 D058_sbas607.gif
Figure 46. IDVDD vs Temperature
ADS127L01 D059_sbas607.gif
INTLDO = 1, LVDD = 1.8 V
Figure 48. Power Dissipation vs Temperature
ADS127L01 D064_sbas607.gif
Inputs shorted, HR mode, LL, 512 kSPS, 32768 samples
Figure 50. Output Spectrum
ADS127L01 D065_sbas607.gif
Inputs shorted, HR mode, LL, 32 kSPS, 32768 samples
Figure 52. Output Spectrum
ADS127L01 D068_sbas607.gif
Inputs shorted, HR mode, LL, 512 kSPS, 32768 samples
Figure 54. Noise Histogram
ADS127L01 D070_sbas607.gif
Inputs shorted, HR mode, LL, 32 kSPS, 32768 samples
Figure 56. Noise Histogram
ADS127L01 D027_sbas607.gif
fIN = 4 kHz, VIN = –20 dBFS, HR mode, WB2, 512 kSPS,
32768 samples
Figure 7. Output Spectrum
ADS127L01 D029_sbas607.gif
fIN = 4 kHz, VIN = –20 dBFS, HR mode, WB1, 512 kSPS,
32768 samples
Figure 9. Output Spectrum
ADS127L01 D031_sbas607.gif
fIN = 4 kHz, VIN = –20 dBFS, LP mode, WB2, 256 kSPS,
32768 samples
Figure 11. Output Spectrum
ADS127L01 D033_sbas607.gif
fIN = 4 kHz, VIN = –20 dBFS, VLP mode, WB2, 128 kSPS,
32768 samples
Figure 13. Output Spectrum
ADS127L01 D035_sbas607.gif
Inputs shorted, LP mode, WB2, 256 kSPS,
32768 samples
Figure 15. Output Spectrum
ADS127L01 D039_SBAS607.gif
HR mode, 0.5 seconds data collection
space
Figure 17. ADC Conversion Noise
ADS127L01 D053_sbas607.gif
Inputs shorted, HR mode
Figure 19. Noise vs VREF
ADS127L01 D055_sbas607.gif
Inputs shorted, HR mode
Figure 21. Noise vs fCLK
ADS127L01 D038_sbas607.gif
WB2, OSR 32
Figure 23. Total Harmonic Distortion vs VIN
ADS127L01 D054_sbas607.gif
fIN = 4 kHz, HR mode
Figure 25. Total Harmonic Distortion vs fCLK
ADS127L01 D072_sbas607.gif
LP mode, fIN = 4 kHz, VIN = –0.5 dBFS
Figure 27. Total Harmonic Distortion Histogram
ADS127L01 D050_sbas607.gif
Figure 29. INL vs Temperature
ADS127L01 D042_sbas607.gif
Inputs shorted
Figure 31. Offset Error Histogram
ADS127L01 D047_sbas607.gif
Inputs shorted
Figure 33. Offset Error vs Temperature
ADS127L01 D043_sbas607.gif
Inputs shorted, 30 devices
Figure 35. Offset Drift Histogram
ADS127L01 D045_sbas607.gif
LP mode, 30 Devices
Figure 37. Gain Drift Histogram
ADS127L01 D061_sbas607.gif
HR mode
Figure 39. Gain Error vs fCLK
ADS127L01 D075_sbas607.gif
HR mode, fCLK = 16.384 MHz
Figure 41. Differential Input Impedance vs Temperature
ADS127L01 D077_SBAS607.gif
HR mode, INTLDO = 0
Figure 43. PSRR vs Power-Supply Frequency
ADS127L01 D057_sbas607.gif
Figure 45. ILVDD vs Temperature
ADS127L01 D063_sbas607.gif
Figure 47. ILVDD vs fCLK
ADS127L01 D060_sbas607.gif
INTLDO = 0
Figure 49. Power Dissipation vs Temperature
ADS127L01 D065_sbas607.gif
Inputs shorted, HR mode, LL, 128 kSPS, 32768 samples
Figure 51. Output Spectrum
ADS127L01 D067_sbas607.gif
Inputs shorted, HR mode, LL, 8 kSPS, 32768 samples
Figure 53. Output Spectrum
ADS127L01 D069_sbas607.gif
Inputs shorted, HR mode, LL, 128 kSPS, 32768 samples
Figure 55. Noise Histogram
ADS127L01 D071_sbas607.gif
Inputs shorted, HR mode, LL, 8 kSPS, 32768 samples
Figure 57. Noise Histogram