JAJSLQ5C April 2021 – September 2022 ADS127L11
PRODUCTION DATA
Return to the Register Map Overview.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MUX[1:0] | ||||||
R-000000b | R/W-00b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:2 | RESERVED | R | 000000b | Reserved |
1:0 | MUX[1:0] | R/W | 00b |
Input multiplexer
selection. These bits select the polarity of the analog input and selects the test modes. See the Analog Input section for details. 00b = Normal input polarity 01b = Inverted input polarity 10b = Offset and noise test: AINP and AINN disconnected, ADC inputs internally shorted to (AVDD1 + AVSS) / 2 11b = Common-mode test: ADC inputs internally shorted and connected to AINP |