JAJSOX0B March 2024 – November 2024 ADS127L18
PRODMIX
SPI Programming is selected by tying the MODE pin to IOVDD. In SPI mode, the hardware mode is disabled and the device is programmed by writing to the SPI registers. Figure 7-45 shows the SPI pins.
The SPI consists of four signals: CS, SCLK, SDI, and SDO (hardware pin functions are subsequently removed from the pin names). The interface operates in a passive mode where SCLK is an input to the device, driven by the host. The interface is compatible to SPI mode 1 (CPOL = 0 and CPHA = 1). In SPI mode 1, SCLK idles low, and data are updated on SCLK rising edges and read on SCLK falling edges. The interface supports full-duplex operation, meaning input data and output data are transmitted simultaneously.
An optional 8-bit CRC value validates data transmission between the host and the device. A 16-bit CRC register value detects register map changes after the initial register data are loaded.