JAJSOX0A March 2024 – June 2024 ADS127L18
ADVANCE INFORMATION
The DCLK pin is the bit-clock output signal that shifts data out from the frame-sync port. DOUT channel data are updated on the falling edge of DCLK and are latched by the host on the rising edge.
The DCLK frequency is derived from the ADC clock through a programmable DCLK divider. See the Clock Operation section for details of the DCLK divider. Make sure the DCLK signal frequency is fast enough to transmit the channel data within one conversion period (FSYNC clock period), otherwise data are lost. Equation 22 shows how to derive the minimum required DCLK frequency.
where:
Table 7-18 shows various examples of DCLK frequencies. The example in the third row is for a 512kSPS data rate, max-speed mode, a TDM factor of 4, and a 24-bit data packet size. The TDM factor equals four channels per DOUT pin. The minimum DCLK signal frequency to shift out the data in one data period is 49.152MHz (512kSPS × 4 × 24). Using 65.536MHz for CLKIN satisfies the minimum DCLK frequency. With the CLK divider = 2, the 32.768MHz CLK frequency is derived for ADC clock operation.
SPEED MODE | DATA RATE (kSPS) |
BITS PER DOUT PIN | DCLK MIN (MHz) |
CLKIN INPUT (MHZ) |
CLK DIVIDER | ADC CLOCK (MHz) |
DCLK DIVIDER | DCLK ACTUAL (MHz) |
---|---|---|---|---|---|---|---|---|
Max | 1365.3 | 48 (2 ch × 24 bits) | 65.536 | 65.536 | 2 | 32.768 | 1 | 65.536 |
Max | 512 | 24 (1 ch × 24 bits) | 12.288 | 32.768 | 1 | 32.768 | 2 | 16.384 |
Max | 512 | 96 (4 ch × 24 bits) | 49.152 | 65.536 | 2 | 32.768 | 1 | 65.536 |
High | 400 | 96 (4 ch × 24 bits) | 38.400 | 51.200 | 2 | 25.600 | 1 | 51.200 |
Mid | 200 | 160 (4 ch × 40 bits) | 32.000 | 38.400 | 3 | 12.800 | 1 | 38.400 |
Low | 50 | 320 (8 ch × 40 bits) | 16.000 | 25.600 | 8 | 3.200 | 1 | 25.600 |
When daisy-chaining the frame-sync port, the maximum DCLK signal frequency is limited; see the Specifications section.