JAJSOX0A March 2024 – June 2024 ADS127L18
ADVANCE INFORMATION
Synchronized control mode simultaneously synchronizes the ADC channels on the rising edge of START. Conversions continue whether START is high or low. Apply a single synchronizing pulse input or a continuous synchronizing clock input to the START pin.
As shown in Figure 7-25, synchronization occurs on the first START rising edge. If the time to the next START rising edge is an n multiple of the conversion period within a ±1 / fCLK window, the ADC does not resynchronize. The value n = 1, 2, 3, and so on. Synchronization does not occur because the ADC conversion period is already synchronized to the period of the START signal. Conversely, if the START signal period is not an n multiple of the conversion period within ± one fCLK cycle, the ADC channels resynchronize. There is no limit to the length of the period when using a continuous synchronizing clock input.
As a result of the digital filter processing time, a phase difference exists between the START signal and the FSYNC output signal. The phase difference varies with the OSR setting of the filter. Figure 7-25 shows the ADC resynchronizing when the period of START input is not equal to an n multiple of the conversion period.