JAJSOX0A March   2024  – June 2024 ADS127L18

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
  7. 6 Parameter Measurement Information
    1. 6.1  Offset Error Measurement
    2. 6.2  Offset Drift Measurement
    3. 6.3  Gain Error Measurement
    4. 6.4  Gain Drift Measurement
    5. 6.5  NMRR Measurement
    6. 6.6  CMRR Measurement
    7. 6.7  PSRR Measurement
    8. 6.8  SNR Measurement
    9. 6.9  INL Error Measurement
    10. 6.10 THD Measurement
    11. 6.11 IMD Measurement
    12. 6.12 SFDR Measurement
    13. 6.13 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs (AINP, AINN)
        1. 7.3.1.1 Input Range
      2. 7.3.2 Reference Voltage (REFP, REFN)
        1. 7.3.2.1 Reference Voltage Range
      3. 7.3.3 Clock Operation
        1. 7.3.3.1 Internal Oscillator
        2. 7.3.3.2 External Clock
      4. 7.3.4 Power Supplies
        1. 7.3.4.1 AVDD1 and AVSS
        2. 7.3.4.2 AVDD2
        3. 7.3.4.3 IOVDD
        4. 7.3.4.4 Power-On Reset (POR)
        5. 7.3.4.5 CAPA and CAPD
      5. 7.3.5 VCM Output Voltage
      6. 7.3.6 GPIO
      7. 7.3.7 Modulator
      8. 7.3.8 Digital Filter
        1. 7.3.8.1 Wideband Filter
      9. 7.3.9 Low-Latency Filter (Sinc)
        1. 7.3.9.1 Sinc4 Filter
        2. 7.3.9.2 Sinc4 + Sinc1 Cascade Filter
        3. 7.3.9.3 Sinc3 Filter
        4. 7.3.9.4 Sinc3 + Sinc1 Filter
    4. 7.4 Device Functional Modes
      1. 7.4.1  Speed Modes
      2. 7.4.2  Synchronization
        1. 7.4.2.1 Synchronized Control Mode
        2. 7.4.2.2 Start/Stop Control Mode
      3. 7.4.3  Digital Filter Settling
      4. 7.4.4  Conversion-Start Delay Time
      5. 7.4.5  Data Averaging
      6. 7.4.6  Calibration
        1. 7.4.6.1 Offset Calibration Registers
        2. 7.4.6.2 Gain Calibration Registers
        3. 7.4.6.3 Calibration Procedure
      7. 7.4.7  Reset
        1. 7.4.7.1 RESET Pin
        2. 7.4.7.2 Reset by SPI Register
        3. 7.4.7.3 Reset by SPI Input Pattern
      8. 7.4.8  Power-Down
      9. 7.4.9  Idle and Standby Modes
      10. 7.4.10 Diagnostics
        1. 7.4.10.1 ERROR Pin and ERR_FLAG Bit
        2. 7.4.10.2 Clock Counter
        3. 7.4.10.3 SCLK Counter
        4. 7.4.10.4 Frame-Sync CRC
        5. 7.4.10.5 SPI CRC
        6. 7.4.10.6 Register Map CRC
        7. 7.4.10.7 Self Test
      11. 7.4.11 Frame-Sync Data Port
        1. 7.4.11.1 FSYNC Pin
        2. 7.4.11.2 DCLK Pin
        3. 7.4.11.3 DOUT Pins
        4. 7.4.11.4 DIN Pins
        5. 7.4.11.5 Time Division Multiplexing
        6. 7.4.11.6 Daisy Chain
        7. 7.4.11.7 Data Packet
        8. 7.4.11.8 STATUS_DP Header
        9. 7.4.11.9 Data Port Timing Adjustment
    5. 7.5 Programming
      1. 7.5.1 Hardware Programming
      2. 7.5.2 SPI Programming
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output (SDO)
      3. 7.5.3 SPI Frame
      4. 7.5.4 SPI Commands
        1. 7.5.4.1 Read Register Command
        2. 7.5.4.2 Write Register Command
      5. 7.5.5 SPI Daisy-Chain
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Driver
      2. 9.1.2 Antialias Filter
      3. 9.1.3 Reference Voltage
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8 Register Map

Table 8-1 lists the SPI register memory map of the ADS127L14 and ADS127L18. Memory addresses 30h and below apply to both the ADS127L14 and the ADS127L18. Memory addresses above 31h apply to channels four through seven of the ADS127L18. Unlisted register addresses are reserved locations and are not to be written to.

Table 8-1 Register Map Summary
Address Register Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
00h DEV_ID xxh DEV_ID[7:0]
01h REV_ID xxh REV_ID[7:0]
02h STATUS 60h RESERVED ALV_FLAG POR_FLAG SPI_ERR REG_ERR ADC_ERR ADDR_ERR SCLK_ERR
03h CLK_CNT 00h CLK_CNT[7:0]
04h GPIO_RD 00h GPIO_RD[7:0]
05h CRC_MSB 00h CRC_MSB[7:0]
06h CRC_LSB 00h CRC_LSB[7:0]
07h CONTROL 00h RESET[5:0] START STOP
08h GEN_CFG1 00h RESERVED DELAY[2:0] VCM REFP_BUF REF_RNG
09h GEN_CFG2 04h AVG_MODE[1:0] RESERVED START_MODE[1:0] SPEED_MODE[1:0] STBY_MODE
0Ah GEN_CFG3 80h OUT_DRV DATA CLK_CNT_EN SPI_STAT_EN SPI_ADDR_EN SCLK_CNT_EN SPI_CRC_EN REG_CRC_EN
0Bh DP_CFG1 20h DP_CRC_EN DP_STAT_EN DP_TDM[1:0] RESERVED DP_DAISY DP_MODE
0Ch DP_CFG2 00h RESERVED DCLK_DIV[1:0] DOUT_DLY[4:0]
0Dh CLK_CFG 00h RESERVED CLK_SEL CLK_DIV[2:0]
0Eh GPIO_WR 00h GPIO_WR[7:0]
0Fh GPIO_DIR 00h GPIO_DIR[7:0]
10h GPIO_EN 00h GPIO_EN[7:0]
11h CH0_CFG1 00h RESERVED CH0_MUX[2:0] CH0_INP_RNG CH0_EX_RNG CH0_BUFN CH0_BUFP
12h CH0_CFG2 00h RESERVED CH0_PWDN CH0_FLTR[4:0]
13h CH0_OFS_MSB 00h CH0_OFFSET_MSB[7:0]
14h CH0_OFS_MID 00h CH0_OFFSET_MID[7:0]
15h CH0_OFS_LSB 00h CH0_OFFSET_LSB[7:0]
16h CH0_GAN_MSB 40h CH0_GAIN_MSB[7:0]
17h CH0_GAN_MID 00h CH0_GAIN_MID[7:0]
18h CH0_GAN_LSB 00h CH0_GAIN_LSB[7:0]
19h CH1_CFG1 00h RESERVED CH1_MUX[2:0] CH1_INP_RNG CH1_EX_RNG CH1_BUFN CH1_BUFP
1Ah CH1_CFG2 00h RESERVED CH1_PWDN CH1_FLTR[4:0]
1Bh CH1_OFS_MSB 00h CH1_OFFSET_MSB[7:0]
1Ch CH1_OFS_MID 00h CH1_OFFSET_MID[7:0]
1Dh CH1_OFS_LSB 00h CH1_OFFSET_LSB[7:0]
1Eh CH1_GAN_MSB 40h CH1_GAIN_MSB[7:0]
1Fh CH1_GAN_MID 00h CH1_GAIN_MID[7:0]
20h CH1_GAN_LSB 00h CH1_GAIN_LSB[7:0]
21h CH2_CFG1 00h RESERVED CH2_MUX[2:0] CH2_INP_RNG CH2_EX_RNG CH2_BUFN CH2_BUFP
22h CH2_CFG2 00h RESERVED CH2_PWDN CH2_FLTR[4:0]
23h CH2_OFS_MSB 00h CH2_OFFSET_MSB[7:0]
24h CH0_OFS_MID 00h CH2_OFFSET_MID[7:0]
25h CH2_OFS_LSB 00h CH2_OFFSET_LSB[7:0]
26h CH2_GAN_MSB 40h CH2_GAIN_MSB[7:0]
27h CH2_GAN_MID 00h CH2_GAIN_MID[7:0]
28h CH2_GAN_LSB 00h CH2_GAIN_LSB[7:0]
29h CH3_CFG1 00h RESERVED CH3_MUX[2:0] CH3_INP_RNG CH3_EX_RNG CH3_BUFN CH3_BUFP
2Ah CH3_CFG2 00h RESERVED CH3_PWDN CH3_FLTR[4:0]
2Bh CH3_OFS_MSB 00h CH3_OFFSET_MSB[7:0]
2Ch CH3_OFS_MID 00h CH3_OFFSET_MID[7:0]
2Dh CH3_OFS_LSB 00h CH3_OFFSET_LSB[7:0]
2Eh CH3_GAN_MSB 40h CH3_GAIN_MSB[7:0]
2Fh CH3_GAN_MID 00h CH3_GAIN_MID[7:0]
30h CH3_GAN_LSB 00h CH3_GAIN_LSB[7:0]
31h CH4_CFG1 00h RESERVED CH4_MUX[2:0] CH4_INP_RNG CH4_EX_RNG CH4_BUFN CH4_BUFP
32h CH4_CFG2 00h RESERVED CH4_PWDN CH4_FLTR[4:0]
33h CH4_OFS_MSB 00h CH4_OFFSET_MSB[7:0]
34h CH4_OFS_MID 00h CH4_OFFSET_MID[7:0]
35h CH4_OFS_LSB 00h CH4_OFFSET_LSB[7:0]
36h CH4_GAN_MSB 40h CH4_GAIN_MSB[7:0]
37h CH4_GAN_MID 00h CH4_GAIN_MID[7:0]
38h CH4_GAN_LSB 00h CH4_GAIN_LSB[7:0]
39h CH5_CFG1 00h RESERVED CH5_MUX[2:0] CH5_INP_RNG CH5_EX_RNG CH5_BUFN CH5_BUFP
3Ah CH5_CFG2 00h RESERVED CH5_PWDN CH5_FLTR[4:0]
3Bh CH5_OFS_MSB 00h CH5_OFFSET_MSB[7:0]
3Ch CH5_OFS_MID 00h CH5_OFFSET_MID[7:0]
3Dh CH5_OFS_LSB 00h CH5_OFFSET_LSB[7:0]
3Eh CH5_GAN_MSB 40h CH5_GAIN_MSB[7:0]
3Fh CH5_GAN_MID 00h CH5_GAIN_MID[7:0]
40h CH5_GAN_LSB 00h CH5_GAIN_LSB[7:0]
41h CH6_CFG1 00h RESERVED CH6_MUX[2:0] CH6_INP_RNG CH6_EX_RNG CH6_BUFN CH6_BUFP
42h CH6_CFG2 00h RESERVED CH6_PWDN CH6_FLTR[4:0]
43h CH6_OFS_MSB 00h CH6_OFFSET_MSB[7:0]
44h CH6_OFS_MID 00h CH6_OFFSET_MID[7:0]
45h CH6_OFS_LSB 00h CH6_OFFSET_LSB[7:0]
46h CH6_GAN_MSB 40h CH6_GAIN_MSB[7:0]
47h CH6_GAN_MID 00h CH6_GAIN_MID[7:0]
48h CH6_GAN_LSB 00h CH6_GAIN_LSB[7:0]
49h CH7_CFG1 00h RESERVED CH7_MUX[2:0] CH7_INP_RNG CH7_EX_RNG CH7_BUFN CH7_BUFP
4Ah CH7_CFG2 00h RESERVED CH7_PWDN CH7_FLTR[4:0]
4Bh CH7_OFS_MSB 00h CH7_OFFSET_MSB[7:0]
4Ch CH7_OFS_MID 00h CH7_OFFSET_MID[7:0]
4Dh CH7_OFS_LSB 00h CH7_OFFSET_LSB[7:0]
4Eh CH7_GAN_MSB 40h CH7_GAIN_MSB[7:0]
4Fh CH7_GAN_MID 00h CH7_GAIN_MID[7:0]
50h CH7_GAN_LSB 00h CH7_GAIN_LSB[7:0]

Table 8-2 shows the access-type codes in this section.

Table 8-2 Register Access-Type Codes
Access Type Code Description
R R Read only
W W Write only
W1C W1C Write 1 to clear
R/W R/W Read or write

8.1 DEV_ID Register (Address = 00h) [Reset = 04h or 06h]

DEV_ID is described in Table 8-3.

Table 8-3 DEV_ID Register Description
Bit Field Type Reset Description
7-0 DEV_ID[7:0] R 00000xx0b Device identification number.
00000100b = ADS127L14
00000110b = ADS127L18

8.2 REV_ID Register (Address = 01h) [Reset = xxh]

REV_ID is described in Table 8-4.

Table 8-4 REV_ID Register Description
Bit Field Type Reset Description
7-0 REV_ID[7:0] R xxxxxxxxb Die revision number.
The die revision number is subject to change during device production without prior notice.

8.3 STATUS Register (Address = 02h) [Reset = 60h]

STATUS is shown in Figure 8-49 and described in Table 8-23.

Figure 8-1 STATUS Register
7 6 5 4 3 2 1 0
RESERVED ALV_FLAG POR_FLAG SPI_ERR REG_ERR ADC_ERR ADDR_ERR SCLK_ERR
R-0b R/W1C-1b R/W1C-1b R/W1C-0b R/W1C-0b R-0b R/W1C-0b R/W1C-0b
Table 8-5 STATUS Register Field Descriptions
Bit Field Type Reset Description
7 RESERVED R 0b Reserved
6 ALV_FLAG R/W1C 1b Analog supply low-voltage flag.
This bit indicates a low-voltage condition of the analog power supplies. Write 1b to reset the flag to detect the next occurrence of a low-voltage condition.
0b = No event from when flag last cleared
1b = Analog power supply low-voltage detected
5 POR_FLAG R/W1C 1b Power-on reset flag.
This bit indicates a device reset occurred at power-on or brownout of the IOVDD power supply or by a user reset operation. Write 1b to reset the flag to detect the next occurrence of a device reset.
0b = No reset from when flag last cleared
1b = Reset occurred
4 SPI_ERR R/W1C 0b SPI received data CRC error.
This bit indicates a CRC error for the SPI received data. Except for this register, register write operations are blocked when the flag is set. Clear the error by writing 1b. The CRC check of the received data is enabled by the SPI_CRC_EN enable bit.
0b = No SPI error
1b = SPI CRC error of the received data
3 REG_ERR R/W1C 0b Register map error.
This bit indicates the contents of the register map have changed after the initial configuration. A 16-bit CRC value written to the CRC_MSB and CRC_LSB registers is required to match the register map CRC value computed by the ADC. The register map range for the CRC calculation is 08h to 50h for both the ADS127L14 and ADS127L18 devices. Clear the error by writing the correct CRC value to CRC_MSB and CRC_LSB, then write 1 to the bit. The register map CRC check is enabled by the REG_CRC_EN register bit.
0b = No error
1b = Register map CRC error
2 ADC_ERR R 0b ADC error.
This bit indicates an internal ADC error. Perform a power cycle or reset the device to clear the error.
0b = No error
1b = ADC error
1 ADDR_ERR R/W1C 0b SPI register address error.
This bit indicates an SPI error when the register read or write address is outside the valid range. The valid address range is 00h to 50h for both ADS127L14 and ADS127L18 devices. Except for the STATUS register, register write operations are blocked when the flag is set. Clear the error by writing 1b. Address error check is enabled by setting SPI_ADDR_EN = 1.
0b = No error
1b = SPI register read/write address outside the valid range
0 SCLK_ERR R/W1C 0b SPI SCLK count error.
This bit indicates an SCLK count error when the number of SPI SCLKs are not a multiple of eight. Except for the STATUS register, register write operations are blocked when the flag is set. Clear the error by writing 1b. SCLK count error check is enabled by setting SCLK_CNT_EN = 1.
0b = No error
1b = Number of SCLK clock cycles is not a multiple of eight

8.4 CLK_CNT Register (Address = 03h) [Reset = 00h]

CLK_CNT is described in Table 8-6.

Table 8-6 CLK_CNT Register Description
Bit Field Type Reset Description
7-0 CLK_CNT[7:0] R 00000000b Clock count value register.
This register is a free-running (roll-over) counter value of the ADC clock. Read the register at known intervals to verify the ADC clock frequency. The clock count value increments at a rate of clock / 32, divided by the CLK_DIV[2:0] divider bits. The clock count is enabled by the CLK_CNT_EN register bit. When enabled, the counter value resets to 00h. When disabled, the count value is 00h.

8.5 GPIO_RD Register (Address = 04h) [Reset = 00h]

GPIO_RD is shown in Figure 8-2 and described in Table 8-7.

Figure 8-2 GPIO_RD Register
7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R-0b R-0b R-0b R-0b R-0b R-0b R-0b R-0b
Table 8-7 GPIO_RD Register Field Descriptions
Bit Field Type Reset Description
7-0 GPIO_RD[7:0] R 00000000b GPIO read data register.
These bits program the GPIO data corresponding to the GPIO input pins. If the GPIO is programmed as an output, the read value also reports the value of the GPIO pin.

8.6 CRC_MSB, CRC_LSB Registers (Addresses = 05h, 06h) [Reset = 00h]

CRC registers described in Table 8-8.

Table 8-8 CRC Registers Description
Name Address Type Reset Description
CRC_MSB
CRC_LSB		 5h
6h		 R/W
R/W		 00h
00h		 Two-byte register map CRC value.
Write a 16-bit CRC value, computed over the register range 08h to 50h for both ADS127L14 and ADS127L18 devices. The register map CRC check is enabled by the REG_CRC_EN bit. The CRC error is reported to the REG_ERR bit of the STATUS register.

8.7 CONTROL Register (Address = 07h) [Reset = 00h]

CONTROL is shown in Figure 8-3 and described in Table 8-9.

Figure 8-3 CONTROL Register
7 6 5 4 3 2 1 0
RESET[5:0] START STOP
R/W-000000b R/W-0b R/W-0b
Table 8-9 CONTROL Register Field Descriptions
Bit Field Type Reset Description
7-2 RESET[5:0] R/W 000000b Software reset.
Write the value of 010110b to these bits for software reset. Make sure the START or STOP bits are also 0b in the same write operation. These bits self-clear and always read 00000b.
1 START R/W 0b START channel conversions.
This bit starts channel conversions by writing 1b. Conversions continue until 1b is written to the STOP bit. This bit also restarts an ongoing conversion. This bit self-clears after being written and always reads 0b. This bit is not functional in synchronized control mode.
0b = No operation
1b = Start or restart conversions on all channels
0 STOP R/W 0b Stop channel conversions.
This bit stops conversions of all channels after the current conversion completes by writing 1b. This bit self-clears after being written and always reads 0b. This bit is not functional in synchronized control mode.
0b = No operation
1b = Stop conversions on all channels

8.8 GEN_CFG1 Register (Address = 08h) [Reset = 00h]

GEN_CFG1 is shown in Figure 8-4 and described in Table 8-10.

Figure 8-4 GEN_CFG1 Register
7 6 5 4 3 2 1
RESERVED DELAY[2:0] VCM REFP_BUF REF_RNG
R-0b R/W-000b R/W-0b R/W-0b R/W-0b
Table 8-10 GEN_CFG1 Register Field Descriptions
Bit Field Type Reset Description
7-6 RESERVED R 0b Reserved
5-3 DELAY[2:0] R/W 000b Conversion start delay time selection.
Select the delay time in number of MODCLK cycles after taking START high (or setting the START bit) to the actual start of channel conversion.
000b = 0
001b = 4
010b = 8
011b = 16
100b = 32
101b = 128
110b = 512
111b = 1024
2 VCM R/W 0b Common-mode voltage output enable.
This bit enables the common-mode voltage output of the VCM pin. The VCM output voltage is equal to (AVDD1 + AVSS) / 2.
0b = VCM disabled
1b = VCM enabled
1 REFP_BUF R/W 0b Reference positive buffer enable.
This bit enables the REFP pin precharge buffer.
0b = Disabled
1b = Enabled
0 REF_RNG R/W 0b Voltage reference range selection.
This bit selects the low or high voltage operating range of the reference input. Program the range to match the actual reference voltage.
0b = Low voltage reference range
1b = High voltage reference range

8.9 GEN_CFG2 Register (Address = 09h) [Reset = 04h]

GEN_CFG2 is shown in Figure 8-5 and described in Table 8-11.

Figure 8-5 GEN_CFG2 Register
7 6 5 4 3 2 1 0
AVG_MODE[1:0] RESERVED START_MODE[1:0] SPEED_MODE[1:0] STBY_MODE
R/W-00b R/W-0b R/W-00b R/W-10b R/W-0b
Table 8-11 GEN_CFG2 Register Field Descriptions
Bit Field Type Reset Description
7-6 AVG_MODE[1:0] R/W 00b Channel data averaging mode.
Select the number of channels to average to form higher resolution data channels from the original data. See the Data Averaging section for more details.
00b = Data averaging disabled
01b = Data averaging in channel groups of two
10b = Data averaging in channel groups of four
11b = Data averaging in channel groups of eight (ADS127L18 only)
5 RESERVED R/W 0b Reserved
4-3 START_MODE[1:0] R/W 00b START mode selection.
These bits program the synchronization mode of the START pin. See the Synchronization section for more details.
00b = Start/stop control mode
01b = Reserved
10b = Synchronized control mode
11b = Reserved
2-1 SPEED_MODE[1:0] R/W 10b Speed mode selection.
These bits program the device speed mode. The clock frequencies listed correspond to the mode. Internal oscillator operation is not available for the max-speed mode.
00b = Low-speed mode (fCLK = 3.2MHz)
01b = Mid-speed mode (fCLK = 12.8MHz)
10b = High-speed mode (fCLK = 25.6MHz)
11b = Max-speed mode (fCLK = 32.768MHz)
0 STBY_MODE R/W 0b Standby mode selection.
This bit enables the standby mode when conversions are stopped. Standby mode reduces power consumption when conversions are stopped.
0b = Idle mode, device fully powered
1b = Standby mode, device is powered down

8.10 GEN_CFG3 Register (Address = 0Ah) [Reset = 80h]

GEN_CFG3 is shown in Figure 8-6 and described in Table 8-12.

Figure 8-6 GEN_CFG3 Register
7 6 5 4 3 2 1 0
OUT_DRV DATA CLK_CNT_EN SPI_STAT_EN SPI_ADDR_EN SCLK_CNT_EN SPI_CRC_EN REG_CRC_EN
R/W-1b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b
Table 8-12 GEN_CFG3 Register Field Descriptions
Bit Field Type Reset Description
7 OUT_DRV R/W 1b Digital output driver power selection.
Select the digital output driver power. For frame-sync frequencies > 50MHz, use the full-power driver mode, otherwise the half-power mode is optional to reduce I/O power consumption.
0b = Full-power driver mode
1b = Half-power driver mode
6 DATA R/W 0b Data resolution selection.
This bit selects the output data resolution.
0b = 24-bit resolution
1b = 16-bit resolution
5 CLK_CNT_EN R/W 0b Clock counter enable.
This bit enables the ADC clock counter register.
0b = Disabled
1b = Enabled
4 SPI_STAT_EN R/W 0b SPI status byte output enable.
Program this bit to include the STATUS register contents with the SPI response field.
0b = STATUS byte disabled
1b = STATUS byte enabled
3 SPI_ADDR_EN R/W 0b SPI register address enable.
This bit enables the SPI address error check. The ADDR_ERR bit of the STATUS register sets if the read or write register address are outside the valid range. The valid address range is 00h to 50h for both ADS127L14 and ADS127L18 devices.
0b = SPI address error disabled
1b = SPI address error enabled
2 SCLK_CNT_EN R/W 0b SCLK count enable.
This bit enables the SPI SCLK count monitor. The number of SCLK clock cycles within an SPI frame must be a multiple of eight. The SCLK_ERR bit of the STATUS register sets if the number of SCLK cycles is not a multiple of 8.
0b = SCLK error disabled
1b = SCLK error enabled
1 SPI_CRC_EN R/W 0b SPI CRC enable.
This bit enables the SPI CRC error check. When enabled, the device verifies the input CRC value against a calculated value. The device also appends a CRC byte to the SPI output data. The SPI_ERR bit of the STATUS byte sets if the input CRC error is in error. Write 1b to the SPI_ERR bit to clear the error.
0b = SPI CRC disabled
1b = SPI CRC enabled
0 REG_CRC_EN R/W 0b Register map CRC enable.
This bit enables the register map CRC error check. Write the 16-bit CRC value to the CRC_MSB and CRC_LSB registers. This value is calculated over registers 08h to 50h for both ADS127L14 and ADS127L18 devices. An internal CRC value is compared to the written value. The REG_ERR bit of the STATUS byte sets if the CRC value is not correct.
0b = Register CRC disabled
1b = Register CRC enabled

DP_CFG1 Register (Address = 0Bh) [Reset = 20h]

DP_CFG1 is shown in Figure 8-7 and described in Table 8-13.

Figure 8-7 DP_CFG1 Register
7 6 5 4 3 2 1 0
DP_CRC_EN DP_STAT_EN DP_TDM[1:0] RESERVED DP_DAISY DP_MODE
R/W-0b R/W-0b R/W-10b R/W-00b R/W-0b R/W-0b
Table 8-13 DP_CFG1 Register Field Descriptions
Bit Field Type Reset Description
7 DP_CRC_EN R/W 0b Data port CRC byte enable.
This bit enables the data port CRC byte. A CRC byte is appended to the end of the channel data.
0b = Data port CRC byte disabled
1b = Data port CRC byte enabled
6 DP_STAT_EN R/W 0b Data port status byte enable.
This bit enables the data port status byte. The status byte is prefixed to the beginning of the channel data.
0b = Data port STATUS byte disabled
1b = Data port STATUS byte enabled
5-4 DP_TDM[1:0] R/W 10b Data port time division multiplexing (TDM) configuration.
These bits select the number of DOUT pins that provide channel data. See the Time Division Multiplexing section for details.
00b = One data output pin
01b = One or two data output pins
10b = Two or four data output pins
11b = Four or eight data output pins
3-2 RESERVED R/W 00b Reserved
1 DP_DAISY R/W 0b Data port daisy-chain mode.
This pin selects between daisy-chain data input mode or repeat data mode.
0b = TDM data mode. DIN data are shifted-in and appended to the original channel data.
1b = Repeat data mode. DIN data are ignored and the original channel data are repeated. The RPT_DATA flag of the STATUS_DP byte indicates repeated data.
0 DP_MODE R/W 0b Data port settled-data mode.
At conversion start and device synchronization, select the data output mode.

0b = Wait for settled data before starting frame-sync signals.
1b = Start frame-sync signals after one conversion cycle beginning with unsettled data. The FLT_RDY bit = 0 until data are settled.

8.11 DP_CFG2 Register (Address = 0Ch) [Reset = 00h]

DP_CFG2 is shown in Figure 8-8 and described in Table 8-14.

Figure 8-8 DP_CFG2 Register
7 6 5 4 3 2 1 0
RESERVED DCLK_DIV[1:0] DOUT_DLY[4:0]
R/W-0b R/W-00b R/W-00000b
Table 8-14 DP_CFG2 Register Field Descriptions
Bit Field Type Reset Description
7 RESERVED R/W 0b Reserved
6-5 DCLK_DIV[1:0] R/W 00b Data port DCLK frequency divider.
These bits select the frame-sync DCLK frequency divider of the controller clock signal source.
00b = Divide by 1
01b = Divide by 2
10b = Divide by 4
11b = Divide by 8
4-0 DOUT_DLY[4:0] R/W 00000b Data port DOUT delay.
This bit field selects the time offset (delay or advance) of DCLK and FSYNC clock signals relative to the DOUT signals. Positive values delay the DCLK and FSYNC signals; negative values delay the DOUT signal. See the Data Port Offset Timing section for details.

8.12 CLK_CFG Register (Address = 0Dh) [Reset = 00h]

CLK_CFG is shown in Figure 8-9 and described in Table 8-15.

Figure 8-9 CLK_CFG Register
7 6 5 4 3 2 1 0
RESERVED CLK_SEL CLK_DIV[2:0]
R/W-0000b R/W-0b R/W-000b
Table 8-15 CLK_CFG Register Field Descriptions
Bit Field Type Reset Description
7-4 RESERVED R/W 0000b Reserved
3 CLK_SEL R/W 0b ADC clock selection.
This bit selects the internal oscillator or external clock operation. The clock signal is divisible by the CLK_DIV[2:0] bits.
0b = Internal oscillator
1b = External clock
2-0 CLK_DIV[2:0] R/W 000b ADC clock divider.
These bits select the clock signal division factor.
000b = Divide by 1
001b = Divide by 2
010b = Divide by 3
011b = Divide by 4
100b = Divide by 8
101b = Divide by 8
110b = Divide by 8
111b = Divide by 8

8.13 GPIO_WR Register (Address = 0Eh) [Reset = 00h]

GPIO_WR is shown in Figure 8-10 and described in Table 8-16.

Figure 8-10 GPIO_WR Register
7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b
Table 8-16 GPIO_WR Register Field Descriptions
Bit Field Type Reset Description
7-0 GPIO_WR[7:0] R/W 00000000b GPIO write data.
This register is the GPIO write data register. Enable the GPIO pin to the output mode for the pin value to update. See the GPIO_RD register to read GPIO data.
0b = GPIO pin is driven logic low
1b = GPIO pin is driven logic high

8.14 GPIO_DIR Register (Address = 0Fh) [Reset = 00h]

GPIO_DIR is shown in Figure 8-11 and described in Table 8-17.

Figure 8-11 GPIO_DIR Register
7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b
Table 8-17 GPIO_DIR Register Field Descriptions
Bit Field Type Reset Description
7-0 GPIO_DIR[7:0] R/W 00000000b GPIO direction.
This register programs the GPIO direction to input or output mode.
0b = The GPIO pin is an output
1b = The GPIO pin is an input

8.15 GPIO_EN Register (Address = 10h) [Reset = 00h]

GPIO_EN is shown in Figure 8-12 and described in Table 8-18.

Figure 8-12 GPIO_EN Register
7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b
Table 8-18 GPIO_EN Register Field Descriptions
Bit Field Type Reset Description
7-0 GPIO_EN[7:0] R/W 00000000b GPIO enable.
This register enables the GPIO function to each pin. When enabled, the GPIO pin overrides all other pin functions. GPIO pin functions are not available in hardware programming mode.
0b = The GPIO pin is disabled
1b = The GPIO pin is enabled

8.16 CHn_CFG1 Registers (Address = Channel Number × 08h + 11h) [Reset = 00h]

Channel n configuration 1 register addresses are shown in Table 8-19. The register bit map is shown in Figure 8-13 and described in Table 8-20.

Table 8-19 CHn_CFG1 Register Addresses
NAME DESCRIPTION ADDRESS
CH0_CFG1 Channel 0 configuration 1 11h
CH1_CFG1 Channel 1 configuration 1 19h
CH2_CFG1 Channel 2 configuration 1 21h
CH3_CFG1 Channel 3 configuration 1 29h
CH4_CFG1 Channel 4 configuration 1 31h
CH5_CFG1 Channel 5 configuration 1 39h
CH6_CFG1 Channel 6 configuration 1 41h
CH7_CFG1 Channel 7 configuration 1 49h
Figure 8-13 CHn_CFG1 Register
7 6 5 4 3 2 1 0
RESERVED CHn_MUX[2:0] CHn_INP_RNG CHn_EX_RNG CHn_BUFN CHn_BUFP
R/W-0b R/W-000b R/W-0b R/W-0b R/W-0b R/W-0b
Table 8-20 CHn_CFG1 Register Field Descriptions
Bit Field Type Reset Description
7 RESERVED R/W 0b Reserved
6-4 CHn_MUX[2:0] R/W 000b Channel input multiplexer selection.
These bits select between the signal input and input test modes. See the Analog Inputs (AINP, AINN) section for details.
000b = Normal input polarity
001b = Reverse input polarity
010b = Offset and noise test: Internal short to mid supply
011b = CMRR test to AINP
100b = CMRR test to AINN
101b = –FS test
110b = +FS test
111b = +FS test
3 CHn_INP_RNG R/W 0b Channel input range selection.
This bit selects the 1x or 2x input range. See the Input Range section for more details.
0b = 1x input range
1b = 2x input range
2 CHn_EX_RNG R/W 0b Channel extended input range selection.
This bit extends the input range by 25%. See the Input Range section for more details. 0b = Disabled
1b = Enabled: The FS range is extended by 25%
1 CHn_BUFN R/W 0b Channel analog input negative buffer enable.
This bit enables the channel AINN precharge buffer.
0b = Disabled
1b = Enabled
0 CHn_BUFP R/W 0b Channel analog input positive buffer enable.
This bit enables the channel AINP precharge buffer.
0b = Disabled
1b = Enabled

8.17 CHn_CFG2 Registers (Address = Channel Number × 08h + 12h) [Reset = 00h]

Channel n configuration 2 register addresses are shown in Table 8-21. The register bit map is shown in Figure 8-14 and described in Table 8-22.

Table 8-21 CHn_CFG2 Register Addresses
NAME REGISTER DESCRIPTION ADDRESS
CH0_CFG2 Channel 0 configuration 2 12h
CH1_CFG2 Channel 1 configuration 2 1Ah
CH2_CFG2 Channel 2 configuration 2 22h
CH3_CFG2 Channel 3 configuration 2 2Ah
CH4_CFG2 Channel 4 configuration 2 32h
CH5_CFG2 Channel 5 configuration 2 3Ah
CH6_CFG2 Channel 6 configuration 2 42h
CH7_CFG2 Channel 7 configuration 2 4Ah
Figure 8-14 CHn_CFG2 Register
7 6 5 4 3 2 1 0
RESERVED CHn_PWDN CHn_FLTR[4:0]
R/W-00b R/W-0b R/W-00000b
Table 8-22 CHn_CFG2 Register Field Descriptions
Bit Field Type Reset Description
7-6 RESERVED R/W 00b Reserved
5 CHn_PWDN R/W 0b Channel power-down mode selection.
When set, the ADC channel is powered down. When powered down, channel data are 0s and FILTRDY always read 0. Data from powered-down channels are included in TDM and channel averaging modes.
0b = Channel powered up
1b = Channel powered down
4-0 CHn_FLTR[4:0] R/W 00000b Channel digital filter and oversampling ratio value selection.
These bits configure the digital filter of the channel. Different values of the data rate are programmable between channels. However, the ratio of OSR among the channels is a power of 2. The filter has five configurations: wideband, sinc4, sinc4 + sinc1, sinc3, and sinc3 + sinc1, each with a range of OSR values.
00000b = Wideband: OSR = 32
00001b = Wideband: OSR = 64
00010b = Wideband: OSR = 128
00011b = Wideband: OSR = 256
00100b = Wideband: OSR = 512
00101b = Wideband: OSR = 1024
00110b = Wideband: OSR = 2048
00111b = Wideband: OSR = 4096
01000b = Sinc4: OSR = 12
01001b = Sinc4: OSR = 16
01010b = Sinc4: OSR = 24
01011b = Sinc4: OSR = 32
01100b = Sinc4: OSR = 64
01101b = Sinc4: OSR = 128
01110b = Sinc4: OSR = 256
01111b = Sinc4: OSR = 512
10000b = Sinc4: OSR = 1024
10001b = Sinc4: OSR = 2048
10010b = Sinc4: OSR = 4096
10011b = Sinc4: OSR = 32 + sinc1: OSR = 2
10100b = Sinc4: OSR = 32 + sinc1: OSR = 4
10101b = Sinc4: OSR = 32 + sinc1: OSR = 10
10110b = Sinc4: OSR = 32 + sinc1: OSR = 20
10111b = Sinc4: OSR = 32 + sinc1: OSR = 40
11000b = Sinc4: OSR = 32 + sinc1: OSR = 100
11001b = Sinc4: OSR = 32 + sinc1: OSR = 200
11010b = Sinc4: OSR = 32 + sinc1: OSR = 400
11011b = Sinc4: OSR = 32 + sinc1: OSR = 1000
11100b = Sinc3: OSR = 26667
11101b = Sinc3: OSR = 32000
11110b = Sinc3: OSR = 32000 + sinc1: OSR = 3
11111b = Sinc3: OSR = 32000 + sinc1: OSR = 5

8.18 CHn Offset Registers [Reset = 000000h]

Channel n offset registers are described in Table 8-19.

Table 8-23 CHn Offset Registers Description
NAME ADDRESS TYPE RESET DESCRIPTION
MSB MID LSB
Channel 0 offset 13h 14h 15h R/W 000000h These registers are three-byte offset registers.
Three registers form the 24-bit offset calibration word of each channel. The offset value is in two's-complement representation and is subtracted from the conversion result. The offset operation precedes the gain operation. In 16-bit mode, conversion data are left-justified to the 24-bit offset value.
Channel 1 offset 1Bh 1Ch 1Dh
Channel 2 offset 23h 24h 25h
Channel 3 offset 2Bh 2Ch 2Dh
Channel 4 offset 33h 34h 35h
Channel 5 offset 3Bh 3Ch 3Dh
Channel 6 offset 43h 44h 45h
Channel 7 offset 4Bh 4Ch 4Dh

8.19 CHn Gain Registers [Reset = 400000h]

Channel n gain registers are described in Table 8-24.

Table 8-24 CHn Gain Registers Description
NAME ADDRESS TYPE RESET DESCRIPTION
MSB MID LSB
Channel 0 gain 16h 17h 18h R/W 400000h These registers are three-byte gain registers.
Three registers form the 24-bit gain calibration word of each channel. The gain value is in straight-binary representation and is normalized to 400000h for gain = 1. The conversion data are multiplied by GAIN[23:0] / 400000h after the offset operation.
Channel 1 gain 1Eh 1Fh 20h
Channel 2 gain 26h 27h 28h
Channel 3 gain 2Eh 2Fh 30h
Channel 4 gain 36h 37h 38h
Channel 5 gain 3Eh 3Fh 40h
Channel 6 gain 46h 47h 48h
Channel 7 gain 4Eh 4Fh 50h