JAJSOX0A March 2024 – June 2024 ADS127L18
ADVANCE INFORMATION
The ADC uses power-supply monitors to detect supply power-on and brownout events. Power-up or power-cycling the IOVDD supply results in device reset. Power-up or power-cycling the analog power supplies do not result in reset.
Figure 7-7 shows the IOVDD and CAPD power-on voltage thresholds. When the voltages are above these thresholds, the ADC is released from reset after a time delay of td(RSSC). If the START pin is high, the ADC starts the conversion process and supplies data to the data port. The POR_FLAG bit of the SPI STATUS register and the PWR_FLAG of the data port header byte indicate the device POR. Write 1b to clear the POR_FLAG to clear the flags and detect the next POR event. The PWR_FLAG of the data port status byte is disabled in hardware programming mode.
Figure 7-8 shows the analog power supply power-on thresholds. Four monitors are used for four supply conditions (AVDD1 – DGND), (AVDD1 – AVSS), (AVDD2 – AVSS), and (CAPA – AVSS). The ALV_FLAG bit (SPI STATUS register) and the PWR_FLAG (data port header byte) are set when any analog power voltage falls below the threshold level. Write 1b to the ALV_FLAG bit to clear the flags to detect the next analog supply low-voltage condition. Power cycling the analog power supplies does not reset the ADC. Because a low voltage on the IOVDD supply also resets the internal analog LDO (CAPA), the analog low-voltage flag (ALV_FLAG) is also set. The PWR_FLAG of the data port status byte is disabled in hardware programming mode.