JAJSOX0A March 2024 – June 2024 ADS127L18
ADVANCE INFORMATION
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
CLOCK | ||||||
tC(CLK) | ADC clock period (programmable) | 1, 2, 3, 4 or 8 / f(CLKIN) or f(OSC) | ||||
FRAME-SYNC DATA PORT | ||||||
tc(FSYNC) | FSYNC period | 1 / f(DATA) | ns | |||
tw(FSYNCH) | Pulse duration, FSYNC high | 0.5 / f(DATA) | ns | |||
tw(FSYNCL) | Pulse duration, FSYNC low | 0.5 / f(DATA) | ns | |||
tp(FSDC) | Propagation delay time, FSYNC rising edge to DCLK falling edge | –1 | 1 | ns | ||
tc(DCLK) | DCLK period | 1, 2, 4, or 8 / f(CLKIN) or f(OSC) | ns | |||
tw(DCLKH) | Pulse duration, DCLK low | 0.5 x tC(DCLK) | ns | |||
tw(DCLKL) | Pulse duration, DCLK high | 0.5 x tC(DCLK) | ns | |||
th(DCDO) | Hold time, DCLK falling edge to previous DOUT invalid | -2 | ns | |||
tp(DCDO) | Propagation delay time, DCLK falling edge to new DOUT valid | 4 | ns | |||
SPI CONFIGURATION PORT | ||||||
tp(CSDO) | Propagation delay time, CS falling edge to SDO driven state | 16 | ns | |||
tp(CSDOZ) | Propagation delay time, CS rising edge to SDO tri-state | 16 | ns | |||
th(SCDO) | Hold time, SCLK rising edge to invalid SDO | 3 | ns | |||
tp(SCDO) | Propagation delay time, SCLK rising edge to valid SDO | 20 | ns | |||
START PIN | ||||||
tp(CLFS1) | Propagation delay time, CLK falling edge after START rising edge to FSYNC and DCLK falling edge (conversion start) | 0 | 4 | ns | ||
tp(CLFS2) | Propagation delay time, CLK rising edge after START rising edge to FSYNC rising edge (first conversion ready) | Unsettled data mode | 1 / fDATA | s | ||
Settled data mode | See the Digital Filter section | |||||
RESET PIN | ||||||
tp(RSFS) | Propagation delay time, RESET rising edge to FSYNC falling edge (ADC ready) | 104 / f(CLK) | ns |