8.3.1 Noise Performance

The ADS1282-HT device offers outstanding noise performance (SNR). SNR depends on the data rate, the PGA setting, and the mode. As the bandwidth is reduced by decreasing the data rate, the SNR improves correspondingly. Similarly, as the PGA gain is increased, the SNR decreases. Table 1 summarizes the noise performance versus data rate, PGA setting, and mode.

8.3.2 Input-Referred Noise

The input-referred noise is related to SNR by Equation 1:

Equation 1.

where

• FSR_RMS = Full-scale range RMS = (VREFP – VREFN)/(2 × √2 × PGA)
• N_RMS = Noise RMS (input-referred)

8.3.3 Idle Tones

The ADS1282-HT modulator incorporates an internal dither signal that randomizes the idle tone energy. Low-level idle tones may still be present, typically –137-dB less than full-scale. The low-level idle tones can be shifted out of the passband with an external offset = 20 mV/PGA. See the Application Information section for the recommended offset circuit.

8.3.4 Operating Mode

The default mode is high-resolution.

8.3.5 Analog Inputs and Multiplexer

Figure 26 shows a diagram of the input multiplexer.

ESD diodes protect the multiplexer inputs. If either input is taken less than AVSS – 0.3 V or greater than AVDD + 0.3 V, the ESD protection diodes may turn on. If these conditions are possible, external Schottky clamp diodes and/or series resistors may be required to limit the input current to safe values (see the Absolute Maximum Ratings).

Also, overdriving one unused input may affect the conversions of the other input. If overdriven inputs are possible, TI recommends clamping the signal with external Schottky diodes.

Figure 26. Analog Inputs and Multiplexer

The specified input operating range of the PGA is shown in Equation 2:

Equation 2.

Absolute input levels (input signal level and common-mode level) should be maintained within these limits for best operation.

The multiplexer connects one of the two external differential inputs to the preamplifier inputs, in addition to internal connections for various self-test modes. Table 2 summarizes the multiplexer configurations for Figure 26.

The typical on-resistance (R_ON) of the multiplexer switch is 30 Ω. When the multiplexer is used to drive an external load on one input by a signal generator on the other input, on-resistance and on-resistance amplitude dependency can lead to measurement errors. Figure 27 shows THD versus load resistance and amplitude. THD improves with high-impedance loads and with lower amplitude drive signals. The data are measured with the circuit from Figure 28 with MUX[2:0] = 011.

Figure 27. THD vs External Load and Signal Magnitude (PGA) (See Figure 28)

Figure 28. Driving an External Load Through the MUX

8.3.6 PGA (Programmable Gain Amplifier)

The PGA of the ADS1282-HT is a low-noise, continuous-time, differential-in/differential-out CMOS amplifier. The gain is programmable from 1 to 64, set by register bits, PGA[2:0]. The PGA differentially drives the modulator through 300-Ω internal resistors. A COG capacitor (10 nF typical) must be connected to CAPP and CAPN to filter modulator sampling glitches. The external capacitor also serves as an anti-alias filter. The corner frequency is given in Equation 3:

Equation 3.

Referring to Figure 29, amplifiers A₁ and A₂ are chopped to remove the offset, offset drift, and the 1/f noise. Chopping moves the effects to ƒ_CLK/128 (8 kHz), which is safely out of the passband. Chopping can be disabled by setting the CHOP register bit = 0. With chopping disabled, the impedance of the PGA increases substantially (>> 1 GΩ). As shown in Figure 30, chopping maintains flat noise density; if chopping is disabled, however, it results in a rising 1/f noise profile.

The PGA has programmable gains from 1 to 64. Table 3 shows the register bit setting for the PGA and resulting full-scale differential range.

The specified output operating range of the PGA is shown in Equation 4:

Equation 4.

PGA output levels (signal plus common-mode) should be maintained within these limits for best operation.

Figure 29. PGA Block Diagram

Figure 30. PGA Noise

8.3.7 ADC

The ADC block of the ADS1282-HT is composed of two sections: a high-accuracy modulator and a programmable digital filter.

8.3.8 Modulator

The high-performance modulator is an inherently-stable, fourth-order, ΔΣ, 2 + 2 pipelined structure, as Figure 31 shows. It shifts the quantization noise to a higher frequency (out of the passband) where digital filtering can easily remove it. The modulator can be filtered either by the on-chip digital filter or by use of post-processing filters.

Figure 31. Fourth-Order Modulator

The modulator first stage converts the analog input voltage into a pulse-code modulated (PCM) stream. When the level of differential analog input (AINP – AINN) is near one-half the level of the reference voltage 1/2 × (VREFP – VREFN), the ‘1’ density of the PCM data stream is at its highest. When the level of the differential analog input is near zero, the PCM ‘0’ and ‘1’ densities are nearly equal. At the two extremes of the analog input levels (+FS and –FS), the ‘1’ density of the PCM streams is approximately 90% and 10%, respectively.

The modulator second stage produces a '1' density data stream designed to cancel the quantization noise of the first stage. The data streams of the two stages are then combined before the digital filter stage, as shown in Equation 5.

Equation 5.

M0[n] represents the most recent first-stage output while M0[n – 1] is the previous first-stage output. When the modulator output is enabled, the digital filter shuts down to save power.

The modulator is optimized for input signals within a 4-kHz passband. As Figure 32 shows, the noise shaping of the modulator results in a sharp increase in noise greater than 6 kHz. The modulator has a chopped input structure that further reduces noise within the passband. The noise moves out of the passband and appears at the chopping frequency (ƒ_CLK / 512 = 8 kHz). The component at 5.8 kHz is the tone frequency, shifted out of band by an external 20 mV/PGA offset. The frequency of the tone is proportional to the applied DC input and is given by PGA × V_IN/0.003 (in kHz).

1-Hz resolution

Figure 32. Modulator Output Spectrum

8.3.9 Modulator Over-Range

The ADS1282-HT modulator is inherently stable, and therefore, has predictable recovery behavior resulting from an input overdrive condition. The modulator does not exhibit self-resetting behavior, which often results in an unstable output data stream.

The ADS1282-HT modulator outputs a 1s density data stream at 90% duty cycle with the positive full-scale input signal applied (10% duty cycle with the negative full-scale signal). If the input is overdriven past 90% modulation, but less than 100% modulation (10% and 0% for negative overdrive, respectively), the modulator remains stable and continues to output the 1s density data stream. The digital filter may or may not clip the output codes to +FS or –FS, depending on the duration of the overdrive. When the input returns to the normal range from a long duration overdrive (worst case), the modulator returns immediately to the normal range, but the group delay of the digital filter delays the return of the conversion result to within the linear range (31 readings for linear phase FIR). 31 additional readings (62 total) are required for completely settled data.

If the inputs are sufficiently overdriven to drive the modulator to full duty cycle, all 1s or all 0s, the modulator enters a stable saturated state. The digital output code may clip to +FS or –FS, again depending on the duration. A small duration overdrive may not always clip the output code. When the input returns to the normal range, the modulator requires up to 12 modulator clock cycles (ƒ_MOD) to exit saturation and return to the linear region. The digital filter requires an additional 62 conversions for fully settled data (linear phase FIR).

In the extreme case of over-range, either input is overdriven, exceeding the voltage of either analog supply voltage plus an internal ESD diode drop. The internal diodes begin to conduct and the signal on the input is clipped. When the input overdrive is removed, the diodes recover quickly. Keep in mind that the input current must be limited to 100-mA peak or 10 mA continuous if an overvoltage condition is possible.

8.3.10 Modulator Input Impedance

The modulator samples the buffered input voltage with an internal capacitor to perform conversions. The charging of the input sampling capacitor draws a transient current from the PGA output. The average value of the current can be used to calculate an effective input impedance of:

The resulting modulator input impedance for CLK = 4.096 MHz is 55 kΩ. The modulator input impedance and the PGA output resistors result in a systematic gain error of –1%. C_S can vary ±20% over production lots, affecting the gain error.

8.3.11 Modulator Over-Range Detection (MFLAG)

The ADS1282-HT has a fast-responding over-range detection that indicates when the differential input exceeds ±100% full scale. The threshold tolerance is ±2.5%.The MFLAG output asserts high when in an over-range condition. As Figure 33 and Figure 34 illustrate, the absolute differential input is compared to 100% of range. The output of the comparator is sampled at the rate of ƒ_MOD / 2, yielding the MFLAG output. The minimum MFLAG pulse width is ƒ_MOD / 2.

Figure 33. Modulator Over-Range Block Diagram

Figure 34. Modulator Over-Range Flag Operation

8.3.12 Voltage Reference Inputs (VREFP, VREFN)

The voltage reference for the ADS1282-HT is the differential voltage between VREFP and VREFN: V_REF = VREFP – VREFN. The reference inputs use a structure similar to that of the analog inputs with the circuitry of the reference inputs shown in Figure 35. The average load presented by the switched capacitor reference input can be modeled with an effective differential impedance of R_EFF = t_SAMPLE / C_IN (t_SAMPLE = 1/ƒ_MOD). The effective impedance of the reference inputs loads the external reference.

Figure 35. Simplified Reference Input Circuit

The ADS1282-HT reference inputs are protected by ESD diodes. In order to prevent these diodes from turning on, the voltage on either input must stay within the range shown in Equation 7:

Equation 7.

The minimum valid input for VREFN is AVSS – 0.1 V and maximum valid input for VREFP is AVDD + 0.1 V.

A high-quality 5 V reference voltage is necessary for achieving the best performance from the ADS1282-HT. Noise and drift on the reference degrade overall system performance, and it is critical that special care be given to the circuitry generating the reference voltages in order to achieve full performance. See Application Information for reference recommendations.

8.3.13 Digital Filter

The digital filter receives the modulator output and decimates the data stream. By adjusting the amount of filtering, tradeoffs can be made between resolution and data rate: filter more for higher resolution, filter less for higher data rate.

The digital filter is comprised of three cascaded filter stages: a variable-decimation, fifth-order sinc filter; a fixed-decimation FIR, low-pass filter (LPF) with selectable phase; and a programmable, first-order, high-pass filter (HPF), as shown in Figure 36.

The output can be taken from one of the three filter blocks, as Figure 36 shows. To implement the digital filter completely off-chip, select the filter bypass setting (modulator output). For partial filtering by the ADS1282-HT, select the sinc filter output. For complete on-chip filtering, activate both the sinc and FIR stages. The HPF can then be included to remove DC and low frequencies from the data. Table 4 shows the filter options.

8.3.13.1 Sinc Filter Stage (Sinx/X)

The sinc filter is a variable decimation rate, fifth-order, low-pass filter. Data are supplied to this section of the filter from the modulator at the rate of ƒ_MOD (ƒ_CLK/4). The sinc filter attenuates the high-frequency noise of the modulator, then decimates the data stream into parallel data. The decimation rate affects the overall data rate of the converter; it is set by the DR[2:0] register bits, as shown in Table 5.

Equation 8 shows the scaled Z-domain transfer function of the sinc filter.

Equation 8.

Table 5. Sinc Filter Data Rates (Clk = 4.096 MHz)

DR[2:0] REGISTER	DECIMATION RATIO (N)	SINC DATA RATE (SPS)
000	128	8000
001	64	16000
010	32	32000
011	16	64000
100	8	128000

Figure 36. Digital Filter and Output Code Processing

Equation 9 shows the frequency domain transfer function of the sinc filter.

Equation 9.

where

• N = Decimation ratio (see Table 5)

The sinc filter has notches (or zeroes) that occur at the output data rate and multiples thereof. At these frequencies, the filter has zero gain. Figure 37 shows the frequency response of the sinc filter and Figure 38 shows the roll-off of the sinc filter.

Figure 37. Sinc Filter Frequency Response

Figure 38. Sinc Filter Roll-Off

8.3.13.2 FIR Stage

The second stage of the ADS1282-HT digital filter is an FIR low-pass filter. Data are supplied to this stage from the sinc filter. The FIR stage is segmented into four sub-stages, as shown in Figure 39. The first two sub-stages are half-band filters with decimation ratios of 2. The third sub-stage decimates by 4 and the fourth sub-stage decimates by 2. The overall decimation of the FIR stage is 32. Two coefficient sets are used for the third and fourth sections, depending on the phase selection. Table 19 (in Device Support) lists the FIR stage coefficients. Table 6 lists the data rates and overall decimation ratio of the FIR stage.

Table 6. Fir Filter Data Rates

DR[2:0] REGISTER	DECIMATION RATIO (N)	FIR DATA RATE (SPS)
000	4096	250
001	2048	500
010	1024	1000
011	512	2000
100	256	4000

Figure 39. Fir Filter Sub-Stages

As shown in Figure 40, the FIR frequency response provides a flat passband to 0.375 of the data rate (±0.003-dB passband ripple). Figure 41 shows the transition from passband to stop band.

Figure 40. FIR Passband Magnitude Response (F_DATA = 500 Hz)

Figure 41. FIR Transition Band Magnitude Response

Although not shown in Figure 41, the passband response repeats at multiples of the modulator frequency (Nƒ_MOD – ƒ₀ and Nƒ_MOD + ƒ₀, where N = 1, 2, and so forth, and ƒ₀ = passband). These image frequencies, if present in the signal and not externally filtered, fold back (or alias) into the passband and cause errors. A low-pass signal filter reduces the effect of aliasing. Often, the RC low-pass filter provided by the PGA output resistors and the external capacitor connected to CAPP and CAPN provides sufficient signal attenuation.

8.3.13.3 Group Delay and Step Response

The FIR block is implemented as a multi-stage FIR structure with selectable linear or minimum phase response. The passband, transition band, and stop band responses of the filters are nearly identical but differ in the respective phase responses.

8.3.13.3.1 Linear Phase Response

Linear phase filters exhibit constant delay time versus input frequency (that is, constant group delay). Linear phase filters have the property that the time delay from any instant of the input signal to the same instant of the output data is constant and is independent of the signal nature. This filter behavior results in essentially zero phase error when analyzing multi-tone signals. However, the group delay and settling time of the linear phase filter are somewhat larger than the minimum phase filter, as shown in Figure 42.

Figure 42. FIR Step Response

8.3.13.3.2 Minimum Phase Response

The minimum phase filter provides a short delay from the arrival of an input signal to the output, but the relationship (phase) is not constant versus frequency, as shown in Figure 43. The filter phase is selected by the PHS bit, as Table 7 shows.

Figure 43. FIR Group Delay (F_DATA = 500 Hz)

Table 7. Fir Phase Selection

PHS BIT	FILTER PHASE
0	Linear
1	Minimum

8.3.13.4 HPF Stage

The last stage of the ADS1282-HT filter block is a first-order HPF implemented as an IIR structure. This filter stage blocks DC signals and rolls off low-frequency components below the cut-off frequency. The transfer function for the filter is shown in Equation 16 of the Device Support.

The high-pass corner frequency is programmed by registers HPF[1:0], in hexadecimal. Equation 10 is used to set the high-pass corner frequency. Table 8 lists example values for the high-pass filter.

Equation 10.

where

• HPF = High-pass filter register value (converted to hexadecimal)
• ω_N = 2πƒ_HP/ƒ_DATA (normalized frequency, radians)
• ƒ_HP = High-pass corner frequency (Hz)
• ƒ_DATA = Data rate (Hz)

Table 8. High-Pass Filter Value Examples

ƒHP (Hz)	DATA RATE (SPS)	HPF[1:0]
0.5	250	0337h
1	500	0337h
1	1000	019Ah

The HPF causes a small gain error, in which case the magnitude of the error depends on the ratio of ƒ_HP/ƒ_DATA. For many common values of (ƒ_HP/ƒ_DATA), the gain error is negligible. Figure 44 shows the gain error of the HPF. The gain error factor is illustrated in Equation 15 (see the Device Support).

Figure 44. HPF Gain Error

Figure 45 shows the first-order amplitude and phase response of the HPF. In the case of applying step inputs or synchronizing, the settling time of the filter should be taken into account.

Figure 45. HPF Amplitude and Phase Response

8.3.14 Master Clock Input (CLK)

The ADS1282-HT requires a clock input for operation. The clock is applied to the CLK pin. The data conversion rate scales directly with the CLK frequency. Power consumption versus CLK frequency is relatively constant (see the Typical Characteristics).

As with any high-speed data converter, a high-quality, low-jitter clock is essential for optimum performance. Crystal clock oscillators are the recommended clock source. Make sure to avoid excess ringing on the clock input; keep the clock trace as short as possible and use a 50-Ω series resistor close to the source.

8.3.15 Synchronization (SYNC Pin and Sync Command)

The ADS1282-HT can be synchronized to an external event, as well as synchronized to other ADS1282-HT devices if the sync event is applied simultaneously.

The ADS1282-HT has two sources for synchronization: the SYNC input pin and the SYNC command. The ADS1282-HT also has two synchronizing modes: Pulse-sync and Continuous-sync. In Pulse-sync mode, the ADS1282-HT synchronizes to a single sync event. In Continuous-sync mode, either a single SYNC event is used to synchronize conversions or a continuous clock is applied to the pin with a period equal to integer multiples of the data rate. When the periods of the sync input and the DRDY output do not match, the ADS1282-HT re-synchronizes and conversions are restarted.

8.3.16 Pulse-Sync Mode

In pulse-sync mode, the ADS1282-HT stops and restarts the conversion process when a sync event occurs (by pin or command). When the sync event occurs, the device resets the internal memory; DRDY goes high (pulse SYNC mode) otherwise in Continuous SYNC mode, DRDY continues to toggle, and after the digital filter has settled, new conversion data are available, as shown in Figure 46 and Pulse-Sync Timing Requirements.

Resynchronization occurs on the next rising CLK edge after the rising edge of the SYNC pin or after the eighth rising SCLK edge for opcode SYNC commands. To be effective, the SYNC opcode should be broadcast to all devices simultaneously.

8.3.17 Continuous-Sync Mode

In Continuous-sync mode, either a single sync pulse or a continuous clock may be applied. When a single sync pulse is applied (rising edge), the device behaves similar to the Pulse-sync mode. However, in this mode, DRDY continues to toggle unaffected but the DOUT output is held low until data are ready, 63 DRDY periods later. When the conversion data are non-zero, new conversion data are ready (as shown in Figure 46).

When a continuous clock is applied to the SYNC pin, the period must be an integral multiple of the output data rate or the device re-synchronizes. Synchronization results in the restarting of the digital filter and an interruption of 63 readings (refer to Pulse-Sync Timing Requirements).

When the sync input is first applied, the device re-synchronizes (under the condition t_SYNC ≠ N / ƒ_DATA). DRDY continues to output but DOUT is held low until the new data are ready. Then, if SYNC is applied again and the period matches an integral multiple of the output data rate, the device freely runs without re-synchronization. The phase of the applied clock and output data rate (DRDY) are not matched because of the initial delay of DRDY after SYNC is first applied. Figure 47 shows the timing for Continuous-Sync mode.

A SYNC clock input should be applied after the Continuous-Sync mode is set. The first rising edge of SYNC then causes a synchronization.

Figure 46. Pulse-Sync Timing, Continuous-Sync Timing With Single Sync

Figure 47. Continuous-Sync Timing With Sync Clock

8.3.18 Reset (RESET Pin and Reset Command)

The ADS1282-HT may be reset in two ways: toggle the RESET pin low or send a Reset command. When using the RESET pin, take it low and hold for at least 2 / ƒ_CLK to force a reset. The ADS1282-HT is held in reset until the pin is released. By command, RESET takes effect on the next rising edge of ƒ_CLK after the eighth rising edge of SCLK of the command. To ensure the Reset command can function, the SPI interface may require resetting itself; see Serial Interface.

In reset, registers are set to default and the conversions are synchronized on the next rising edge of CLK. New conversion data are available, as shown in Figure 48 and Reset Timing Requirements.

Figure 48. Reset Timing

8.3.19 Power-Down (PWDN Pin and Standby Command)

There are two ways to power-down the ADS1282-HT: take the PWDN pin low or send a Standby command. When the PWDN pin is pulled low, the internal circuitry is disabled to minimize power and the contents of the register settings are reset.

In power-down, the device outputs remain active and the device inputs must not float. When the Standby command is sent, the SPI port and the configuration registers are kept active. Figure 49 and Pulse-Sync Timing Requirements show the timing.

Figure 49. PWDN Pin and Wake-Up Command Timing
(Pulse-Sync Timing Requirements Shows t_DR)

8.3.20 Power-On Sequence

The ADS1282-HT has three power supplies: AVDD, AVSS, and DVDD. Figure 50 shows the power-on sequence of the ADS1282-HT. The power supplies can be sequenced in any order. The supplies [the difference of (AVDD – AVSS) and DVDD] generate an internal reset whose outputs are summed to generate a global internal reset. After the supplies have crossed the minimum thresholds, 2¹⁶ ƒ_CLK cycles are counted before releasing the internal reset. After the internal reset is released, new conversion data are available, as shown in Figure 50 and Pulse-Sync Timing Requirements.

Figure 50. Power-On Sequence

8.3.21 Serial Interface

A serial interface is used to read the conversion data and access the configuration registers. The interface consists of three basic signals: SCLK, DIN, and DOUT. An additional output, DRDY, transitions low in Read Data Continuous mode when data are ready for retrieval. Figure 51 shows the connection when multiple converters are used.

Figure 51. Interface for Multiple Devices

8.3.21.4 Data Ready (DRDY)

DRDY is an output; when it transitions low, this transition indicates new conversion data are ready, as shown in Figure 52. When reading data by the continuous mode, the data must be read within four CLK periods before DRDY goes low again or the data are overwritten with new conversion data. When reading data by the command mode, the read operation can overlap the occurrence of the next DRDY without data corruption.

Figure 52. DRDY With Data Retrieval

DRDY resets high on the first falling edge of SCLK. Figure 52 and Figure 53 show the function of DRDY with and without data readback, respectively.

If data are not retrieved (no SCLK provided), DRDY pulses high for four ƒ_CLK periods during the update time, as shown in Figure 53.

Figure 53. DRDY With No Data Retrieval

8.3.22 Data Format

The ADS1282-HT provides 32 bits of conversion data in binary twos complement format, as shown in Table 9. The LSB of the data is a redundant sign bit: '0' for positive numbers and '1' for negative numbers. However, when the output is clipped to +FS, the LSB = 1; when the output is clipped to –FS, the LSB = 0. If desired, the data readback may be stopped at 24 bits. In sinc filter mode, the output data are scaled by 1/2.

Table 9. Ideal Output Code Versus Input Signal

INPUT SIGNAL VIN (AINP – AINN)			32-BIT IDEAL OUTPUT CODE(1)
			FIR FILTER	SINC FILTER(2)
			7FFFFFFFh	(3)
			7FFFFFFEh	3FFFFFFFh
			00000002h	00000001h
0			00000000h	00000000h
			FFFFFFFFh	FFFFFFFFh
			80000001h	C0000000h
			80000000h	(3)

1. Excludes effects of noise, linearity, offset, and gain errors.
2. Due to the reduction in oversampling ratio (OSR) related to the sinc filter high data rates, full 32-bit available resolution is reduced.
3. In sinc filter mode, the output does not clip at half-scale code when the full-scale range is exceeded.

8.3.23 Reading Data

The ADS1282-HT has two ways to read conversion data: Read Data Continuous and Read Data By Command.

8.3.23.2 Read Data by Command

The Read Data Continuous mode is stopped by the SDATAC command. In this mode, conversion data are read by command. In the Read Data By Command mode, a read data command must be sent to the device for each data conversion (as shown in Figure 55). When the read data command is received (on the eighth SCLK rising edge), data are available to read only when DRDY goes low (t_DR). When DRDY goes low, conversion data appear on DOUT. The data may be read on the rising edge of SCLK.

Figure 54. Read Data Continuous

Figure 55. Read Data By Command, Rdata (T_DDPD Timing Is Given In Read Data Timing Requirements)

8.3.24 One-Shot Operation

The ADS1282-HT can perform very power-efficient, one-shot conversions using the STANDBY command while under software control. Figure 73 shows this sequence. First, issue the STANDBY command to set the Standby mode.

When ready to make a measurement, issue the WAKEUP command. Monitor DRDY; when it goes low, the fully settled conversion data are ready and may be read directly in Read Data Continuous mode. Afterwards, issue another STANDBY command. When ready for the next measurement, repeat the cycle starting with another WAKEUP command.

8.4.1 Modulator Output Mode

The modulator digital stream output is accessible directly, bypassing and disabling the internal digital filter. The modulator output mode is activated by setting the CONFIG0 register bits FILTR[1:0] = 00. Pins M0 and M1 then become the modulator data outputs and the MCLK becomes the modulator clock output. When not in the modulator mode, these pins are inputs and must be tied.

The modulator output is composed of three signals: one output for the modulator clock (MCLK) and two outputs for the modulator data (M0 and M1). The modulator clock output rate is ƒ_MOD (ƒ_CLK / 4). The SYNC input resets the MCLK phase, as shown in Figure 56. The SYNC input is latched on the rising edge of CLK. The MCLK resets and the next rising edge of MCLK occurs five CLK periods later.

The modulator output data are two bits wide, which must be merged together before being filtered. Use the time domain equation of Equation 5 to merge the data outputs.

1.

NOINDENT:

MCLK = ƒ_CLK / 4.

Figure 56. Modulator Mode Timing

8.5.1 Commands

The commands listed in Table 10 control the operation of the ADS1282-HT. Most commands are stand-alone (that is, 1 byte in length); the register reads and writes require a second command byte in addition to the actual data bytes.

A delay of 24 ƒ_CLK cycles between commands and between bytes within a command is required, starting from the last SCLK rising edge of one command to the first SCLK rising edge of the following command. This delay is shown in Figure 57.

In Read Data Continuous mode, the ADS1282-HT places conversion data on the DOUT pin as SCLK is applied. As a consequence of the potential conflict of conversion data on DOUT and data placed on DOUT resulting from a register or Read Data By Command operation, it is necessary to send a STOP Read Data Continuous command before Register or Data Read By Command. The STOP Read Data Continuous command disables the direct output of conversion data on the DOUT pin.

1. t_SCLKDLY = 24/ƒ_CLK (min).

Figure 57. Consecutive Commands

8.5.1.2 STANDBY: Standby Mode

This command places the ADS1282-HT into Standby mode. In Standby, the device enters a reduced power state where a low quiescent current remains to keep the register settings and SPI interface active. For complete device shutdown, take the PWDN pin low (register settings are not saved). To exit Standby mode, issue the WAKEUP command. The operation of Standby mode is shown in Figure 58.

Figure 58. Standby Command Sequence

8.5.1.11 GANCAL: Gain Calibration

This command performs a gain calibration. The inputs to the converter should have a stable DC input, preferably close to (but not exceeding) positive full-scale. The gain calibration register updates after this operation. See Calibration Commands for more details.

Figure 59. Read Register Data ( Shows t_DLY)

Figure 60. Write Register Data ( Shows t_DLY)

Equation 11. t_DLY = 24 / ƒ_CLK

8.5.2 Calibration Commands

Calibration commands may be sent to the ADS1282-HT to calibrate the conversion data. The values of the offset and gain calibration registers are internally written to perform calibration. The appropriate input signals must be applied to the ADS1282-HT inputs before sending the commands. Use slower data rates to achieve more consistent calibration results; this effect is a byproduct of the lower noise that these data rates provide. Also, if calibrating at power-on, be sure the reference voltage is fully settled.

Figure 61 shows the calibration command sequence. After the analog input voltage (and reference) have stabilized, send the Stop Data Continuous command followed by the SYNC and Read Data Continuous commands. 64 data periods later, DRDY goes low. After DRDY goes low, send the Stop Data Continuous, then the Calibrate command followed by the Read Data Continuous command. After 16 data periods, calibration is complete and conversion data may be read at this time. The SYNC input must remain high during the calibration sequence.

The calibration commands apply to specific PGA settings. If the PGA is changed, recalibration is necessary. Calibration is bypassed in the sinc filter mode.

8.5.2.2 GANCAL Command

The GANCAL command performs a gain calibration. Before sending the GANCAL command, a DC input signal must be applied that is in the range of, but not exceeding, positive or negative full-scale. After the signal has stabilized, the command can be sent. The ADS1282-HT averages 16 readings, then computes the value that compensates for the gain error. The gain correction value is then written to the FSC register. The contents of the GANCAL register may be subsequently read or written. While the gain calibration command corrects for gain errors greater than 1 (gain correction <1), to avoid input overload, the analog inputs cannot exceed full-scale range. The gain calibration should be performed after the offset calibration.

Figure 61. Offset/Gain Calibration Timing

8.5.3 User Calibration

System calibration of the ADS1282-HT can be performed without using the calibration commands. This procedure requires the calibration values to be externally calculated and then written to the calibration registers. The steps for this procedure are:

1. Set the OFSCAL[2:0] register = 0h and GANCAL[2:0] = 400000h. These values set the offset and gain registers to 0 and 1, respectively.
2. Apply a zero differential input to the input of the system. Wait for the system to settle and then average n output readings. Higher numbers of averaged readings result in more consistent calibration. Write the averaged value to the OFC register.
3. Apply a differential positive or negative DC signal, or an AC signal, less than the full-scale input to the system. Wait for the system to settle and then average the n output readings.

The value written to the FSC registers is calculated by Equation 12.

DC signal calibration is shown in Equation 12. The expected output code is based on 31-bit output data.

Equation 12.

For AC signal calibration, use an RMS value of collected data (as shown in Equation 13).

Equation 13.

8.5.4 Configuration Guide

After RESET or power-on, the registers can be configured using the following procedure:

1. Reset the serial interface. Before using the serial interface, it may be necessary to recover the serial interface (undefined I/O power-up sequencing may cause false SCLK detection). To reset the SPI interface, toggle the RESET pin or, when in Read Data Continuous mode, hold SCLK low for 64 DRDY periods.
2. Configure the registers. The registers are configured by either writing to them individually or as a group. Software may be configured in either mode. The SDATAC command must be sent before register read/write operations to cancel the Read Data Continuous mode.
3. Verify register data. The register may be read back for verification of device communications.
4. Set the data mode. After register configuration, the device may be configured for Read Data Continuous mode, either by the Read Data Continuous command or configured in Read Data By Register mode using SDATAC command.
5. Synchronize readings. Whenever SYNC is high, the ADS1282-HT freely runs the data conversions. To stop and re-sync the conversions, take SYNC low and then high.
6. Read data. If the Read Data Continuous mode is active, the data are read directly after DRDY falls by applying SCLK pulses. If the Read Data Continuous mode is inactive, the data can only be read by Read Data By Command. The Read Data opcode command must be sent in this mode to read each conversion result (DRDY only asserts after each read data command is sent).

8.6.1 ADS1282-HT Register Map Information

Collectively, the registers contain all the information needed to configure the part, such as data rate, filter selection, calibration, and so forth. The registers are accessed by the RREG and WREG commands. The registers can be accessed individually or as a block of registers by sending or receiving consecutive bytes. After a register write operation the ADC resets, resulting in an interruption of 63 readings.

8.6.2 ID Register

8.6.3 Configuration Registers

8.6.4 HPF1 and HPF0

These two bytes (high-byte and low-byte, respectively) set the corner frequency of the high-pass filter.

8.6.5 OFC2, OFC1, OFC0

These three bytes set the offset calibration value.

8.6.6 FSC2, FSC1, FSC0

These three bytes set the full-scale calibration value.

8.6.7 Offset and Full-Scale Calibration Registers

The conversion data can be scaled for offset and gain before yielding the final output code. As shown in Figure 74, the output of the digital filter is first subtracted by the offset register (OFC) and then multiplied by the full-scale register (FSC). Equation 14 shows the scaling:

Equation 14.

The values of the offset and full-scale registers are set by writing to them directly, or they are set automatically by calibration commands.

The offset and full-scale calibrations apply to specific PGA settings. When the PGA changes, the contents of these registers may have to be recalculated. Calibration is bypassed in the sinc filter mode.

1.

NOINDENT:

See Figure 49 and for time to new data.

Figure 73. One-Shot Conversions Using the Standby Command

Figure 74. Calibration Block Diagram