JAJSHV4C January   2014  – August 2019 ADS1283

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
    1.     概略回路図
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Performance
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Inputs and Multiplexer
      2. 8.3.2 Programmable Gain Amplifier (PGA)
      3. 8.3.3 Analog-to-Digital Converter (ADC)
        1. 8.3.3.1 Modulator
          1. 8.3.3.1.1 Modulator Overrange
          2. 8.3.3.1.2 Modulator Input Impedance
          3. 8.3.3.1.3 Modulator Overrange Detection (MFLAG)
          4. 8.3.3.1.4 Offset
          5. 8.3.3.1.5 Voltage Reference Inputs (VREFP, VREFN)
        2. 8.3.3.2 Digital Filter
          1. 8.3.3.2.1 Sinc Filter Stage (sinx / x)
          2. 8.3.3.2.2 FIR Stage
          3. 8.3.3.2.3 Group Delay and Step Response
            1. 8.3.3.2.3.1 Linear Phase Response
            2. 8.3.3.2.3.2 Minimum Phase Response
          4. 8.3.3.2.4 HPF Stage
      4. 8.3.4 Master Clock Input (CLK)
    4. 8.4 Device Functional Modes
      1. 8.4.1  Synchronization (SYNC PIN and SYNC Command)
        1. 8.4.1.1 Pulse-Sync Mode
        2. 8.4.1.2 Continuous-Sync Mode
      2. 8.4.2  Reset (RESET Pin and Reset Command)
      3. 8.4.3  Power-Down (PWDN Pin and STANDBY Command)
      4. 8.4.4  Power-On Sequence
      5. 8.4.5  DVDD Power Supply
      6. 8.4.6  Serial Interface
        1. 8.4.6.1 Chip Select (CS)
        2. 8.4.6.2 Serial Clock (SCLK)
        3. 8.4.6.3 Data Input (DIN)
        4. 8.4.6.4 Data Output (DOUT)
        5. 8.4.6.5 Serial Port Auto Timeout
        6. 8.4.6.6 Data Ready (DRDY)
      7. 8.4.7  Data Format
      8. 8.4.8  Reading Data
        1. 8.4.8.1 Read-Data-Continuous Mode
        2. 8.4.8.2 Read-Data-By-Command Mode
      9. 8.4.9  One-Shot Operation
      10. 8.4.10 Offset and Full-Scale Calibration Registers
        1. 8.4.10.1 OFC[2:0] Registers
        2. 8.4.10.2 FSC[2:0] Registers
      11. 8.4.11 Calibration Commands (OFSCAL and GANCAL)
        1. 8.4.11.1 OFSCAL Command
        2. 8.4.11.2 GANCAL Command
      12. 8.4.12 User Calibration
    5. 8.5 Programming
      1. 8.5.1 Commands
        1. 8.5.1.1  SDATAC Requirements
        2. 8.5.1.2  WAKEUP: Wake-Up From Standby Mode
        3. 8.5.1.3  STANDBY: Standby Mode
        4. 8.5.1.4  SYNC: Synchronize the Analog-to-Digital Conversion
        5. 8.5.1.5  RESET: Reset the Device
        6. 8.5.1.6  RDATAC: Read Data Continuous
        7. 8.5.1.7  SDATAC: Stop Read Data Continuous
        8. 8.5.1.8  RDATA: Read Data by Command
        9. 8.5.1.9  RREG: Read Register Data
        10. 8.5.1.10 WREG: Write to Register
        11. 8.5.1.11 OFSCAL: Offset Calibration
        12. 8.5.1.12 GANCAL: Gain Calibration
    6. 8.6 Register Maps
      1. 8.6.1 Register Descriptions
        1. 8.6.1.1 ID_CFG: ID_Configuration Register (address = 00h) [reset =x0h]
        2. 8.6.1.2 CONFIG0: Configuration Register 0 (address = 01h) [reset = 52h]
        3. 8.6.1.3 CONFIG1: Configuration Register 1 (address = 02h) [reset = 08h]
        4. 8.6.1.4 HPF0 and HPF1 Registers
          1. 8.6.1.4.1 HPF0: High-Pass Filter Corner Frequency, Low Byte (address = 03h) [reset = 32h]
          2. 8.6.1.4.2 HPF1: High-Pass Filter Corner Frequency, High Byte (address = 04h) [reset = 03h]
        5. 8.6.1.5 OFC0, OFC1, OFC2 Registers
          1. 8.6.1.5.1 OFC0: Offset Calibration, Low Byte (address = 05h) [reset = 00h]
          2. 8.6.1.5.2 OFC1: Offset Calibration, Mid Byte (address = 06h) [reset = 00h]
          3. 8.6.1.5.3 OFC2: Offset Calibration, High Byte (address = 07h) [reset = 00h]
        6. 8.6.1.6 FSC0, FSC1, FSC2 Registers
          1. 8.6.1.6.1 FSC0: Full-Scale Calibration, Low Byte (address = 08h) [reset = 00h]
          2. 8.6.1.6.2 FSC1: Full-Scale Calibration, Mid Byte (address = 09h) [reset = 00h]
          3. 8.6.1.6.3 FSC2: Full-Scale Calibration, High Byte (address = 0Ah) [reset = 40h]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Geophone Interface
      2. 9.2.2 Digital Interface
    3. 9.3 Initialization Set Up
  10. 10デバイスおよびドキュメントのサポート
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 コミュニティ・リソース
    3. 10.3 商標
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 Glossary
  11. 11メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.1 Noise Performance

The ADS1283 offers outstanding signal-to-noise ratio (SNR). The SNR depends on the ADC data rate and the PGA gain selected. As the bandwidth is reduced by decreasing the data rate, the SNR improves correspondingly. Similarly, as gain is increased, the input-referred noise decreases. The PGA noise is independent of gain; therefore, as the gain increases, the input range correspondingly decreases, resulting in decreased SNR.

The ADS1283 provides a chop feature that reduces the PGA 1/f noise. See the Programmable Gain Amplifier (PGA) section for more information about chopping. Table 1 summarizes the SNR and input noise voltage with the CHOP bit enabled. Disabling the CHOP bit results in increased low-frequency noise, particularly evident with high PGA gains and lower sample rates. Table 2 summarizes SNR and input noise voltage with CHOP disabled.

Table 1. Signal-to-Noise Ratio (dB) and Input Noise (µV), CHOP Bit Enabled

DATA RATE (SPS) PGA (SNR, dB)(1) PGA (Input-Referred Noise, µV RMS)
1 2 4 8 16 32 64 1 2 4 8 16 32 64
250 130 129 129 127 125 119 114 0.59 0.30 0.16 0.10 0.07 0.06 0.06
500 127 126 126 124 122 116 111 0.84 0.43 0.23 0.14 0.09 0.09 0.08
1000 124 123 123 121 119 113 108 1.19 0.60 0.32 0.20 0.13 0.12 0.11
2000 121 120 120 118 116 110 105 1.68 0.86 0.46 0.28 0.18 0.17 0.16
4000 117 117 117 115 113 107 102 2.40 1.22 0.66 0.40 0.26 0.25 0.23
(1) Typical values at T = +25°C and VREF = 5 V. SNR values rounded to the nearest dB. Number of ADC conversions used in the analysis varied to maintain measurement bandwidth = 0.1 Hz to 0.413 × data rate. Note that SNR and input noise data of ADS1283A applies to PGA = 1, 4, and 16 only.

Table 2. Signal-to-Noise Ratio (dB) and Input Noise (µV), CHOP Bit Disabled

DATA RATE (SPS) PGA (SNR, dB)(1) PGA (Input-Referred Noise, µV RMS)
1 2 4 8 16 32 64 1 2 4 8 16 32 64
250 129 128 125 120 116 110 104 0.63 0.37 0.26 0.21 0.18 0.17 0.18
500 126 125 123 119 114 108 103 0.87 0.47 0.31 0.25 0.21 0.21 0.20
1000 123 123 121 117 114 108 102 1.20 0.65 0.39 0.30 0.22 0.22 0.22
2000 120 120 119 116 112 107 101 1.69 0.91 0.51 0.37 0.26 0.25 0.25
4000 117 117 116 114 111 105 99 2.41 1.24 0.70 0.46 0.33 0.31 0.30
(1) Typical values at T = +25°C and VREF = 5 V. SNR values rounded to the nearest dB. Number of ADC conversions used in the analysis varied to maintain measurement bandwidth = 0.1 Hz to 0.413 × data rate. Note that SNR and input noise data of ADS1283A applies to PGA = 1, 4, and 16 only.

Input-referred noise is related to SNR by Equation 1:

Equation 1. ADS1283 q_snr_20log_bas418.gif

where

  • FSRRMS = Full-scale range RMS = VREF / (2 × √2 × PGA)
  • NRMS = Noise (RMS, input-referred)