デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
ADS1285 は、プログラマブル・ゲイン・アンプ (PGA) と有限インパルス応答 (FIR) フィルタを備えた 32 ビット、低消費電力の A/D コンバータ (ADC) です。この ADC は、低ノイズで高精度のデジタル化と長いバッテリ動作時間が求められる地震関連機器の厳しい要件に合わせて設計されています。
低ノイズ PGA により、外付けアンプを使用せずに、ジオフォンやトランス結合のハイドロフォンを直接接続できます。
この ADC は、高分解能のデルタ-シグマ (ΔΣ) 変調器と、位相応答を設定できる FIR フィルタを内蔵しています。ハイパス・フィルタは、DC および低周波数成分を信号から除去します。サンプル・レート・コンバータは、7ppb の分解能でクロック周波数誤差を補償します。
電力モードの選択により、消費電力とダイナミック・レンジを最適化できます。PGA バイパス動作により、消費電力をさらに低減できます。
この ADC は小型の 5mm × 5mm VQFN パッケージで供給され、–40℃~+85℃の周囲温度範囲で仕様が規定されています。
部品番号 | パッケージ | 本体サイズ (公称) |
---|---|---|
ADS1285 | RHB (VQFN、32) | 5.00mm × 5.00mm |
Changes from Revision * (May 2022) to Revision A (December 2022)
PIN | FUNCTION | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | AIN1P | Analog input | Channel 1 positive input |
2 | AIN1N | Analog input | Channel 1 negative input |
3 | AIN2P | Analog input | Channel 2 positive input |
4 | AIN2N | Analog input | Channel 2 negative input |
5 | CAPP | Analog internal | PGA positive capacitor. Connect a 10-nF C0G capacitor across CAPP and CAPN. |
6 | CAPN | Analog internal | PGA negative capacitor. Connect a 10-nF C0G capacitor across CAPP and CAPN. |
7 | CAPBP | Analog internal | Buffer positive capacitor. Connect a 47-nF C0G capacitor to AVSS. |
8 | CAPBN | Analog internal | Buffer negative capacitor. Connect a 47-nF C0G capacitor to AVSS. |
9 | CAPC | Analog internal | Charge-pump capacitor. Connect a 4.7-nF, minimum 10-V rated capacitor to AGND. |
10 | AVSS | Analog supply | PGA negative analog supply. See the Section 9.3.1 section for details. |
11 | AVDD1 | Analog supply | PGA positive analog supply. See the Section 9.3.1 section for details. |
12 | AVDD2 | Analog supply | Modulator analog supply. See the Section 9.3.1 section for details. |
13 | AGND | Analog ground | Analog ground |
14 | CAPI | Analog internal | Input bias capacitor. Connect a 100-nF ceramic capacitor to AGND. |
15 | GPIO0 | Digital I/O | General-purpose I/O |
16 | GPIO1 | Digital I/O | General-purpose I/O |
17 | CAPD | Analog output | Digital low-dropout regulator (LDO) output. Connect a 220-nF ceramic capacitor to DGND. |
18 | DGND | Ground | Digital ground |
19 | IOVDD | Digital supply | Digital I/O power supply. See the Section 8.3.4 section for details. |
20 | CLK | Digital input | ADC clock input |
21 | CS | Digital input | Serial interface select, active low |
22 | SCLK | Digital input | Serial interface clock |
23 | DIN | Digital input | Serial interface data in |
24 | DOUT | Digital output | Serial interface data out |
25 | DRDY | Digital output | Data ready, active low |
26 | SYNC | Digital input | ADC synchronization, active high |
27 | RESET | Digital input | ADC reset, active low |
28 | PWDN | Digital input | ADC power down, active low |
29 | REFN | Analog input | Negative reference input. See the Section 8.3.3 section for details. |
30 | REFP | Analog input | Positive reference input. See the Section 8.3.3 section for details. |
31 | CAPR | Analog internal | Reference bias capacitor. Connect a 100-nF ceramic capacitor to AVSS. |
32 | AVSS | Analog supply | PGA negative supply |
Thermal pad | Connect the thermal pad to AVSS. Thermal vias placed in the printed circuit board (PCB) land are optional for placement of bottom side components. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Power supply voltages | AVDD1 to AVSS | –0.3 | 5.5 | V |
AVSS to AGND | –2.8 | 0.3 | ||
AVDD2 to AGND | –0.3 | 5.5 | ||
AVDD2 to AVSS | –0.3 | 5.5 | ||
IOVDD to DGND | –0.3 | 3.9 | ||
IOVDD to DGND (IOVDD connected to CAPD) | –0.3 | 2.2 | ||
Grounds | AGND to DGND | – 0.3 | 0.3 | V |
Analog input voltage | AIN1P, AIN1N, AIN2P, AIN2N, REFP, REFN | AVSS – 0.3 | AVDD1 + 0.3 | V |
Digital input voltage |
CLK, DIN, SCLK, CS, GPIO0, GPIO1, SYNC, RESET, PWDN | DGND – 0.3 | IOVDD + 0.3 | V |
Input current | Continuous, any digital or analog pin (2) | –10 | 10 | mA |
Temperature | Junction, TJ | 150 | °C | |
Storage, Tstg | –60 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | 2000 | V |
Charged-device model (CDM), per JEDEC JESD22-C101(2) | 1000 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
POWER SUPPLY | ||||||
Analog power supplies | AVDD1 to AVSS | 3 | 5.25 | V | ||
AVDD1 to AGND | 2.375 | V | ||||
AVSS to AGND | –2.625 | 0 | ||||
AVDD2 to AGND | 2.375 | 5.25 | ||||
AVDD2 to AVSS | 5.25 | |||||
Digital power supply | IOVDD to DGND | 2.7 | 3.6 | V | ||
IOVDD connected to CAPD | 1.65 | 1.95 | ||||
ANALOG INPUTS | ||||||
VIN | Differential input voltage VIN = VAINP – VAINN |
Reference voltage = 5 V | ±VREF / (2 × Gain) | V | ||
Reference voltage = 4.096 V | ±VREF / (1.6384 × Gain) | |||||
Reference voltage = 2.5 V | ±VREF / Gain | |||||
Absolute input voltage | Buffer operation | AVSS + 0.1 | AVDD1 – 0.1 | V | ||
PGA operation | AVSS + 1.1 | AVDD1 – 0.85 | ||||
Absolute output voltage | Buffer operation | AVSS + 0.1 | AVDD1 – 0.1 | V | ||
PGA operation | AVSS + 0.15 | AVDD1 – 0.15 | ||||
Calibration range (1) | 6% | FSR | ||||
VOLTAGE REFERENCE INPUT | ||||||
VREFN | Negative reference input | AVSS – 0.05 | V | |||
VREFP | Positive reference input | AVDD1 + 0.1 | V | |||
VREF | VREF = VREFP – VREFN | Reference voltage = 5 V | 4.9 | 5 | AVDD1 – AVSS + 0.1 | V |
Reference voltage = 4.096 V | 4.0 | 4.096 | 4.2 | V | ||
Reference voltage = 2.5 V | 2.4 | 2.5 | 2.6 | V | ||
DIGITAL INPUTS | ||||||
VINL | Low-level input voltage | 0.2 × IOVDD | V | |||
VINH | High-level input voltage | 0.8 × IOVDD | V | |||
fCLK | Clock input frequency | High-power mode | 6 | 8.192 | 8.3 | MHz |
Mid-power mode | 6 | 8.192 | 8.3 | |||
Low-power mode | 3 | 4.096 | 4.15 | |||
TEMPERATURE | ||||||
TA | Ambient temperature | Operational | –50 | 85 | °C | |
Specification | –40 | 85 |
THERMAL METRIC(1) | ADS1285 | UNIT | |
---|---|---|---|
RHB (VQFN) | |||
32 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 30 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 19.4 | °C/W |
RθJB | Junction-to-board thermal resistance | 10.9 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.2 | °C/W |
ψJB | Junction-to-board characterization parameter | 10.8 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 1.8 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
ANALOG INPUTS | |||||||
Input mux on-resistance | Input 1 to input 2 cross connection | 60 | Ω | ||||
PGA OPERATION | |||||||
IB | PGA Input bias current | High-power mode | 45 | nA | |||
IOS | PGA Input offset current | High-power mode | ±3 | nA | |||
PGA Gain | 1, 2, 4, 8, 16, 32, 64 | V/V | |||||
en-PGA | PGA Input voltage noise density | High-power mode | PGA Gain = 16 | 5.5 | nV/√Hz | ||
Mid-power mode | 7 | ||||||
Low-power mode | 7 | ||||||
in-PGA | PGA Input current noise density | Differential | 2.5 | pA/√Hz | |||
Antialias filter frequency | 30 | kHz | |||||
BUFFER OPERATION | |||||||
IB | Input current | High-power mode | VIN = 2.5 V | ±1.2 | µA | ||
Mid-power mode | ±1.2 | ||||||
Low-power mode | ±0.3 | ||||||
DC PERFORMANCE | |||||||
en | Noise | See Noise Performance section for details | |||||
VOS | Offset error | PGA operation | –350/gain - 10 | ±30/gain + 5 | 350/gain + 10 | µV | |
Buffer operation | –600 | ±50 | 600 | ||||
After calibration | ±1 | ||||||
Offset error drift | PGA operation | 0.5/gain | µV/°C | ||||
Buffer operation | 1 | ||||||
Gain error | PGA operation, gain = 1 | –0.05% | ±0.02% | 0.05% | |||
After calibration | 2 | ppm | |||||
Buffer operation | –0.07% | ±0.05% | 0.07% | ||||
Gain match | Relative to PGA gain = 1 | –0.2% | ±0.06% | 0.2% | |||
Gain drift | All PGA gains | 2 | ppm/°C | ||||
CMRR | Common-mode rejection ratio | f = 60 Hz | 104 | 120 | dB | ||
PSRR | Power-supply rejection ratio | AVDD2 | At dc | 80 | 95 | dB | |
AVSS, AVDD1 | 85 | 110 | dB | ||||
IOVDD | 100 | 120 | dB | ||||
AC PERFORMANCE | |||||||
en-MOD | Modulator voltage noise density | VREF = 4.096 V | 25 | nV/√Hz | |||
THD | Total harmonic distortion | High-power mode, VREF = 2.5 V, AVDD1 = 3.3 V, AVSS = 0 V, fIN = 31.25 Hz, VIN = –0.5 dBFS |
Buffer operation | –123 | -114 | dB | |
PGA gain = 2 | –119 | ||||||
PGA gain = 4 | –125 | -116 | |||||
PGA gain = 8 | –124 | ||||||
PGA gain = 16 | –123 | -116 | |||||
PGA gain = 32 and 64 | –125 | ||||||
Mid-power mode, VREF = 2.5 V, AVDD1 = 3.3 V, AVSS = 0 V, fIN = 31.25 Hz, VIN = –0.5 dBFS |
Buffer operation | –122 | -113 | dB | |||
PGA gain = 2 | –120 | ||||||
PGA gain = 4 | –125 | -118 | |||||
PGA gain = 8 | –124 | ||||||
PGA gain = 16 | –123 | -115 | |||||
PGA gain = 32 and 64 | –125 | ||||||
Low-power mode, VREF = 2.5 V, AVDD1 = 3.3 V, AVSS = 0 V, fIN = 31.25 Hz, VIN = –0.5 dBFS |
Buffer operation | –124 | -117 | dB | |||
PGA gain = 2 | –122 | ||||||
PGA gain = 4 | –124 | -116 | |||||
PGA gain = 8 | –125 | ||||||
PGA gain = 16 | –123 | -115 | |||||
PGA gain = 32 and 64 | –124 | ||||||
High-power mode, VREF = 4.096 V, AVDD1 = 5 V, AVSS = 0 V, fIN = 31.25 Hz, VIN = –0.5 dBFS |
Buffer operation | –119 | -114 | dB | |||
PGA gain = 1 | –119 | -111 | |||||
PGA gain = 2 | –125 | ||||||
PGA gain = 4 | –122 | -114 | |||||
PGA gain = 8 | –118 | ||||||
PGA gain = 16 | –117 | -111 | |||||
PGA gain = 32 and 64 | –125 | ||||||
Mid-power mode, VREF = 4.096 V, AVDD1 = 5 V, AVSS = 0 V, fIN = 31.25 Hz, VIN = –0.5 dBFS |
Buffer operation | –119 | -112 | dB | |||
PGA gain = 1 | –119 | -111 | |||||
PGA gain = 2 | –125 | ||||||
PGA gain = 4 | –124 | -115 | |||||
PGA gain = 8 | –119 | ||||||
PGA gain = 16 | –117 | -111 | |||||
PGA gain = 32 and 64 | –124 | ||||||
Low-power mode, VREF = 4.096 V, AVDD1 = 5 V, AVSS = 0 V, fIN = 31.25 Hz, VIN = –0.5 dBFS |
Buffer operation | –123 | -117 | dB | |||
PGA gain = 1 | –121 | -115 | |||||
PGA gain = 2 | –124 | ||||||
PGA gain = 4 | –125 | -115 | |||||
PGA gain = 8 | –122 | ||||||
PGA gain = 16 | –121 | -113 | |||||
PGA gain = 32 and 64 | –123 | ||||||
SFDR | Spurious-free dynamic range | fIN = 31.25 Hz, VIN = –0.5 dBFS | 115 | dB | |||
Crosstalk | fIN = 31.25 Hz, VIN = –0.5 dBFS | –140 | dB | ||||
VOLTAGE REFERENCE INPUT | |||||||
Reference input current | High-power mode | 110 | µA/V | ||||
Mid-power mode | 110 | ||||||
Low-power mode | 80 | ||||||
FIR DIGITAL FILTER | |||||||
fDATA | Data rate | High-power mode | 250 | 4000 | SPS | ||
Mid-power mode | 250 | 4000 | |||||
Low-power mode | 125 | 2000 | |||||
Pass-band ripple | –0.003 | 0.003 | dB | ||||
Pass-band (–0.01 dB) | 0.375 × fDATA | Hz | |||||
Bandwidth (–3 dB) | 0.413 × fDATA | Hz | |||||
Stop band | 0.5 × fDATA | Hz | |||||
Stop-band attenuation (1) | 135 | dB | |||||
Group delay | Minimum phase filter, at dc | 5 / fDATA | s | ||||
Linear phase filter | 31/ fDATA | ||||||
Settling time (latency) | Minimum phase filter | 62 / fDATA | s | ||||
Linear phase filter | 62 / fDATA | ||||||
IIR DIGITAL FILTER | |||||||
High-pass corner frequency | 0.1 | 10 | Hz | ||||
SAMPLE RATE CONVERTER | |||||||
Clock compensation range | –244 | 244 | ppm of fCLK | ||||
Resolution | 7.45 | ppb of fCLK | |||||
DIGITAL INPUT/OUTPUT | |||||||
VOH | High-level output voltage | IOH = 1 mA | 0.8 × IOVDD | V | |||
VOL | Low-level output voltage | IOL = –1 mA | 0.2 × IOVDD | V | |||
Ilkg | Input leakage | –1 | 1 | μA | |||
POWER SUPPLY | |||||||
IAVDD1, IAVSS |
AVDD1, AVSS current | High-power mode AVDD1 = 3.3 V |
PGA operation | 1.4 | mA | ||
Buffer operation | 0.25 | ||||||
Mid-power mode AVDD1 = 3.3 V |
PGA operation | 0.85 | mA | ||||
Buffer operation | 0.25 | ||||||
Low-power mode AVDD1 = 3.3 V |
PGA operation | 0.8 | mA | ||||
Buffer operation | 0.2 | ||||||
High-power mode AVDD1 = 5 V |
PGA operation | 1.5 | 1.85 | mA | |||
Buffer operation | 0.35 | 0.45 | |||||
Mid-power mode AVDD1 = 5 V |
PGA operation | 0.9 | 1.2 | mA | |||
Buffer operation | 0.35 | 0.45 | |||||
Low-power mode AVDD1 = 5 V |
PGA operation | 0.85 | 1.1 | mA | |||
Buffer operation | 0.25 | 0.45 | |||||
Power-down mode | 1 | 5 | µA | ||||
IAVDD2 | AVDD2 current | High-power mode | AVDD2 = 2.5 V | 1.2 | 1.5 | mA | |
Mid-power mode | 1.2 | 1.5 | |||||
Low-power mode | 0.7 | 0.85 | |||||
Power-down mode | 1 | 5 | µA | ||||
IIOVDD | IOVDD current | High-power mode | 0.43 | 0.6 | mA | ||
Mid-power mode | 0.43 | 0.6 | |||||
Low-power mode | 0.24 | 0.4 | |||||
Power-down mode | 1 | 10 | μA | ||||
Standby mode | 200 | ||||||
IOVDD additional current | High-power mode | Sample rate converter operation | 1.2 | mA | |||
Mid-power mode | 1.2 | ||||||
Low-power mode | 0.6 | ||||||
Pd | Power dissipation (2) | High-power mode AVDD1 = 3.3 V AVDD2 = 2.5 V |
PGA operation | 8.3 | mW | ||
Buffer operation | 4.5 | ||||||
Mid-power mode AVDD1 = 3.3 V AVDD2 = 2.5 V |
PGA operation | 6.5 | mW | ||||
Buffer operation | 4.5 | ||||||
Low-power mode AVDD1 = 3.3 V AVDD2 = 2.5 V |
PGA operation | 4.8 | mW | ||||
Buffer operation | 2.8 | ||||||
High-power mode AVDD1 = 5 V AVDD2 = 2.5 V |
PGA operation | 11.5 | 14.1 | mW | |||
Buffer operation | 5.3 | 6.7 | |||||
Mid-power mode AVDD1 = 5 V AVDD2 = 2.5 V |
PGA operation | 8.3 | 10.8 | mW | |||
Buffer operation | 5.3 | 6.7 | |||||
Low-power mode AVDD1 = 5 V AVDD2 = 2.5 V |
PGA operation | 6.4 | 8.4 | mW | |||
Buffer operation | 3.4 | 5.1 |