JAJSHV5B June 2017 – August 2019 ADS1287
PRODUCTION DATA.
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ID[3:0] | MODE[2:1] | OFFSET | RESERVED | ||||
R-x | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | ID[3:0] | R | --- | Factory-programmed identification bits (read-only).
The ID bits are subject to change without notification. |
3:2 | MODE[2:1] | R/W | 0h | Operating mode.
These bits must be set the same as the MODE[0] bit; see the CONFIG0 register. 00: Low-power mode 01: Reserved 10: Reserved 11: High-resolution mode |
1 | OFFSET | R/W | 0h | 50-mV offset option.
See the Offset section. 0: Offset disabled (default) 1: Offset enabled |
0 | RESERVED | R/W | 0h | Reserved.
Always write 0. |