JAJSHV5B June 2017 – August 2019 ADS1287
PRODUCTION DATA.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SYNC | MODE[0] | DR[2:0] | PHASE | FILTR[1:0] | |||
R/W-0h | R/W-1h | R/W-2h | R/W-0h | R/W-2h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | SYNC | R/W | 0h | Synchronization mode configuration bit.
0: Pulse-sync mode (default) 1: Continuous-sync mode |
6 | MODE[0] | R/W | 1h | Operating mode bit.
This bit must be set in coordination with MODE2 and MODE1 bits; see Table 22. 0: Low-power mode 1: High-resolution mode |
5:3 | DR[2:0] | R/W | 2h | Data rate bits.
000: 62.5 SPS 001: 125 SPS 010: 250 SPS (default) 011: 500 SPS 100: 1000 SPS |
2 | PHASE | R/W | 0h | FIR phase response bit.
0: Linear phase (default) 1: Minimum phase |
1:0 | FILTR[1:0] | R/W | 2h | Digital filter configuration bits.
00: Reserved 01: LPF sinc filter only 10: LPF sinc + LPF FIR filter (default) 11: LPF sinc + LPF FIR + HPF filter |