JAJSI11B October 2019 – February 2021 ADS131M08
PRODUCTION DATA
MIN | NOM | MAX | UNIT(1) | ||
---|---|---|---|---|---|
1.65 V ≤ DVDD ≤ 2.0 V | |||||
tw(CLL) | Pulse duration, CLKIN low | 49 | ns | ||
tw(CLH) | Pulse duration, CLKIN high | 49 | ns | ||
tc(SC) | SCLK period | 64 | ns | ||
tw(SCL) | Pulse duration, SCLK low | 32 | ns | ||
tw(SCH) | Pulse duration, SCLK high | 32 | ns | ||
td(CSSC) | Delay time, first SCLK rising edge after CS falling edge | 16 | ns | ||
td(SCCS) | Delay time, CS rising edge after final SCLK falling edge | 10 | ns | ||
tw(CSH) | Pulse duration, CS high | 20 | ns | ||
tsu(DI) | Setup time, DIN valid before SCLK falling egde | 5 | ns | ||
th(DI) | Hold time, DIN valid after SCLK falling edge | 10 | ns | ||
tw(RSL) | Pulse duration, SYNC/RESET low to generate device reset | 2048 | tCLKIN | ||
tw(SYL) | Pulse duration, SYNC/RESET low for synchronization | 1 | 2047 | tCLKIN | |
tsu(SY) | Setup time, SYNC/RESET valid before CLKIN rising edge | 10 | ns | ||
2.7 V ≤ DVDD ≤ 3.6 V | |||||
tw(CLL) | Pulse duration, CLKIN low | 49 | ns | ||
tw(CLH) | Pulse duration, CLKIN high | 49 | ns | ||
tc(SC) | SCLK period | 40 | ns | ||
tw(SCL) | Pulse duration, SCLK low | 20 | ns | ||
tw(SCH) | Pulse duration, SCLK high | 20 | ns | ||
td(CSSC) | Delay time, first SCLK rising edge after CS falling edge | 16 | ns | ||
td(SCCS) | Delay time, CS rising edge after final SCLK falling edge | 10 | ns | ||
tw(CSH) | Pulse duration, CS high | 15 | ns | ||
tsu(DI) | Setup time, DIN valid before SCLK falling egde | 5 | ns | ||
th(DI) | Hold time, DIN valid after SCLK falling edge | 10 | ns | ||
tw(RSL) | Pulse duration, SYNC/RESET low to generate device reset | 2048 | tCLKIN | ||
tw(SYL) | Pulse duration, SYNC/RESET low for synchronization | 1 | 2047 | tCLKIN | |
tsu(SY) | Setup time, SYNC/RESET valid before CLKIN rising edge | 10 | ns |