JAJSPW8 データシート | TI.com

JAJSPW8E march 2011 – february 2023 ADS4222 , ADS4225 , ADS4226 , ADS4242 , ADS4245 , ADS4246

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RGC|64
- MPQF125F

サーマルパッド・メカニカル・データ

RGC|64
- QFND123N

発注情報

7.12.4 ADS4226

At T_A = 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock, 1.5-V_PP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, High-Performance Mode disabled, 0-dB gain, DDR LVDS output interface, and 32k point FFT, unless otherwise noted.

Figure 7-70 FFT for 20-MHz Input Signal

Figure 7-72 FFT for Two-Tone Input Signal

Figure 7-74 SFDR vs Input Frequency

Figure 7-76 SNR vs Input Frequency (CMOS)

Figure 7-78 SINAD vs Gain and Input Frequency

Figure 7-80 Performance vs Input Amplitude

Figure 7-82 Performance vs Input Common-Mode Voltage

Figure 7-84 Performance vs DRVDD Supply Voltage

Figure 7-86 Performance vs Input Clock Amplitude

Figure 7-71 FFT for 170-MHz Input Signal

Figure 7-73 FFT for Two-Tone Input Signal

Figure 7-75 SNR vs Input Frequency

Figure 7-77 SFDR vs Gain and Input Frequency

Figure 7-79 Performance vs Input Amplitude

Figure 7-81 Performance vs Input Common-Mode Voltage

Figure 7-83 SNR vs Temperature and AVDD Supply

Figure 7-85 Performance vs Input Clock Amplitude

Figure 7-87 Performance vs Input Clock Duty Cycle