JAJSPW8 データシート | TI.com

JAJSPW8E march 2011 – february 2023 ADS4222 , ADS4225 , ADS4226 , ADS4242 , ADS4245 , ADS4246

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RGC|64
- MPQF125F

サーマルパッド・メカニカル・データ

RGC|64
- QFND123N

発注情報

7.12.1 ADS4246

At T_A = 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock, 1.5-V_PP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, High-Performance Mode disabled, 0-dB gain, DDR LVDS output interface, and 32k point FFT, unless otherwise noted.

Figure 7-6 FFT for 20-MHz Input Signal

Figure 7-8 FFT for 300-MHz Input Signal

Figure 7-10 FFT for Two-Tone Input Signal

Figure 7-12 SNR vs Input Frequency

Figure 7-14 SFDR vs Gain and Input Frequency

Figure 7-16 Performance vs Input Amplitude

Figure 7-18 Performance vs Input Common-Mode Voltage

Figure 7-20 SFDR vs Temperature and AVDD Supply

Figure 7-22 Performance vs DRVDD Supply Voltage

Figure 7-24 Performance vs Input Clock Amplitude

Figure 7-26 Integrated Nonlinearity

Figure 7-7 FFT for 170-MHz Input Signal

Figure 7-9 FFT for Two-tone Input Signal

Figure 7-11 SFDR vs Input Frequency

Figure 7-13 SNR vs Input Frequency (CMOS)

Figure 7-15 SINAD vs Gain and Input Frequency

Figure 7-17 Performance vs Input Amplitude

Figure 7-19 Performance vs Input Common-Mode Voltage

Figure 7-21 SNR vs Temperature and AVDD Supply

Figure 7-23 Performance vs Input Clock Amplitude

Figure 7-25 Performance vs Input Clock Duty Cycle

Figure 7-27 Output Noise Histogram (With Inputs Shorted to VCM)